(WIP) feat: compiler #71
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@lonerapier Do you want to chat about this at all? It's brainworming me at the moment. Maybe we could cook together? |
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absolutely love this direction. API based DSL will save a lot of errors that arise due to language parsing, and it's so easy to extend than separate language as in #60.
@Autoparallel would love to help in any way possible.
src/compiler/mod.rs
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| pub mod dsl; | ||
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| pub struct Wire { |
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how will wires have input and output? maybe a better name could be Constraint?
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oh yeah, that is better. I think I was trippin'
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Actually, the input and output here were going to be the gates or inputs this wire was connected to.
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Oh, got it. I got confused then. I remember previously it was names as Connection Maybe that made more sense? IDK, i'll let you cook.
src/compiler/mod.rs
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| pub struct Circuit { | ||
| pub gates: DiGraph<Gate, Wire>, |
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maybe instead of picturing a circuit as graph, a simple tuple of (Gate, Constraint) that extends to rows and column in execution trace?
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I think I do want to trash the graph, this is a relic of my first pass. I will remove it for now.
One thing I also want to do is impl a nice Display for our circuits, so that's on my mind as far as this goes.
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I made a small little DSL that will allow you to write Rust to generate the arithmetic expressions. My goal is to get this to yield circuits that can then be used along with our polynomial modules and etc.