padding to 32

pine64 · Jul 24, 2021 · f2b7fc3 · f2b7fc3
1 parent a3a7308
commit f2b7fc3
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/script/reglib.py b/script/reglib.py
@@ -97,6 +97,8 @@ def genHeader(self):
                     padId = padId + 1
                 s.extend(ident(i.genHeader(), 2, '\t'))
                 currentBit = i.msb + 1
+            if currentBit != 32:
+                s.append(f'\t\tuint32_t pad{padId} : {32 - currentBit};')
 
             s.extend([
                 "\t};",
@@ -290,6 +292,12 @@ def FieldBit(name, bit, len=1):
         context.r.addField(name, (~(((2**len)-1)<<bit) & 0xFFFFFFFF))
     else:
         print("You are not in any register")
+
+def FieldRename(lsb, name):
+    if context.r:
+        for f in context.r.fields:
+            if f.lsb == lsb:
+                f.name = name
 
 def HasField(addr):
     if context.r: