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Merge pull request openhwgroup#2425 from XavierAubert/cv32e40p/dev_bn…
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…l_ww19_PR

CV32E40Pv2 Verification update Week 19 PR
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@MikeOpenHWGroup
MikeOpenHWGroup authored May 10, 2024
2 parents db5591f + 3bb659a commit 88586e7
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Showing 23 changed files with 356 additions and 30 deletions.
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42 changes: 35 additions & 7 deletions cv32e40p/env/corev-dv/cv32e40p_instr_test_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -364,7 +364,13 @@ package cv32e40p_instr_test_pkg;
instr.push_back($sformatf("srli x%0d, x%0d, 13", cfg_corev.gpr[0], cfg_corev.gpr[0]));
instr.push_back($sformatf("andi x%0d, x%0d, 0x3", cfg_corev.gpr[0], cfg_corev.gpr[0])); //Check MSTATUS.FS bit
instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3));
instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push
if (cfg_corev.enable_nested_interrupt) begin
// fixme: refer workaround_1
instr.push_back($sformatf("# bne x%0d, x%0d, 2f # workaround for mstatus.FS during nested irq", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push
end
else begin
instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push
end

// Reserve space from kernel stack to save all 32 FPR + FCSR
instr.push_back($sformatf("addi x%0d, x%0d, -%0d", sp, sp, 33 * (XLEN/8)));
Expand Down Expand Up @@ -442,18 +448,31 @@ package cv32e40p_instr_test_pkg;

// Pop MSTATUS.FS from kernel stack
instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg_corev.gpr[0], 0, sp));

// Restore MSTATUS.FS
instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); //Clear FS
instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[1]));
instr.push_back($sformatf("csrrc x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name()));
instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[0]));
instr.push_back($sformatf("csrrs x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name()));
if (cfg_corev.enable_nested_interrupt) begin
// fixme: refer workaround_1
// do not clear FS
end
else begin
instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); //Clear FS
instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[1]));
instr.push_back($sformatf("csrrc x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name()));
instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[0]));
instr.push_back($sformatf("csrrs x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name()));
end

// Restore kernel stack pointer
instr.push_back($sformatf("addi x%0d, x%0d, %0d", sp, sp, 1 * (XLEN/8)));

instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3));
instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR
if (cfg_corev.enable_nested_interrupt) begin
// fixme: refer workaround_1
instr.push_back($sformatf("# bne x%0d, x%0d, 2f # workaround for mstatus.FS during nested irq", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR
end
else begin
instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR
end

randcase
1: load_instr = (FLEN == 32) ? "flw" : "fld";
Expand All @@ -478,6 +497,15 @@ package cv32e40p_instr_test_pkg;

end

// fixme: the irq handling logic flow need to be rework to consider nested irq scenario for fpu csr such as FS.
// workaround_1 for MSTATUS.FS during nested irq by assuming FS always DIRTY prior irq handling.
if (cfg_corev.enable_nested_interrupt) begin
// always set FS to DIRTY prior mret
instr.push_back($sformatf("li x%0d, 0x3 # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1]));
instr.push_back($sformatf("slli x%0d, x%0d, 13 # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1], cfg_corev.gpr[1]));
instr.push_back($sformatf("csrrs x0, mstatus, x%0d # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1]));
end

load_instr = (XLEN == 32) ? "lw" : "ld";
// Pop user mode GPRs from kernel stack
for(int i = 1; i < 32; i++) begin
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2 changes: 1 addition & 1 deletion cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv
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Expand Up @@ -65,7 +65,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component;
ignore_bins cur_fpu_wo_rs3 = !binsof(cp_cur_is_fpu_instr) intersect {`RV32ZFINX_INSTR_W_RS3};

`define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \
ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL};
ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS1};

`define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \
ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS2};
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5 changes: 4 additions & 1 deletion cv32e40p/env/uvme/uvme_cv32e40p_macros.sv
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Expand Up @@ -32,8 +32,11 @@
TB_OPCODE_OP, TB_OPCODE_OPIMM, TB_OPCODE_LOAD, TB_OPCODE_JALR, TB_OPCODE_JAL, TB_OPCODE_AUIPC, TB_OPCODE_LUI, \
OPCODE_CUSTOM_0, OPCODE_CUSTOM_1, OPCODE_CUSTOM_2, OPCODE_CUSTOM_3

`define RV32_OPCODE_WITH_NO_RS1 \
TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_FENCE

`define RV32_OPCODE_WITH_NO_RS2 \
TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM
TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM,OPCODE_CUSTOM_0

`define RV32F_INSTR_WITH_FS1 \
TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, TB_INS_FSQRT, \
Expand Down
30 changes: 15 additions & 15 deletions cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml
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Expand Up @@ -21,6 +21,18 @@ builds:

# List of tests
tests:
corev_rand_interrupt_wfi:
build: uvmt_cv32e40p
description: corev_rand_interrupt_wfi
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_interrupt_wfi_mem_stress:
build: uvmt_cv32e40p
description: corev_rand_interrupt_wfi_mem_stress
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000"

corev_rand_debug:
build: uvmt_cv32e40p
description: corev_rand_debug
Expand Down Expand Up @@ -69,23 +81,11 @@ tests:
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

# corev_rand_interrupt_nested:
# build: uvmt_cv32e40p
# description: corev_rand_interrupt_nested
# dir: cv32e40p/sim/uvmt
# cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_interrupt_wfi:
corev_rand_interrupt_nested:
build: uvmt_cv32e40p
description: corev_rand_interrupt_wfi
description: corev_rand_interrupt_nested
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_interrupt_wfi_mem_stress:
build: uvmt_cv32e40p
description: corev_rand_interrupt_wfi_mem_stress
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000"
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

# list of corev_rand_pulp_hwloop_debug - START

Expand Down
9 changes: 8 additions & 1 deletion cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do
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Expand Up @@ -30,7 +30,10 @@ coverage exclude -line 226 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t
coverage exclude -line 227 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0}
coverage exclude -line 228 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0}
coverage exclude -line 229 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0}
coverage exclude -line 292 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0}
coverage exclude -line 287 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.}
coverage exclude -line 287 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.}
coverage exclude -line 288 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.}
coverage exclude -feccondrow 292 4 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0}
coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.}
coverage exclude -line 416 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.}
coverage exclude -line 424 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.}
Expand Down Expand Up @@ -377,3 +380,7 @@ coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t
coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[13]} -comment {this part of leading zero counter is not used.}
coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[14]} -comment {this part of leading zero counter is not used.}
coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[15]} -comment {this part of leading zero counter is not used.}
coverage exclude -feccondrow 211 4 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (row4) is unreachable. Proven with Formal. We never apu_en_1 and regfile_alu_we at the same time.}
coverage exclude -feccondrow 237 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (Row5) is unreachable. Proven with Formal.}
coverage exclude -feccondrow 241 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (Row5) is unreachable. Proven with Formal.}
coverage exclude -feccondrow 387 22 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {unreachable in FPU config. It only could be hit with Z config for apu_read_dep_for_jalr.}
2 changes: 1 addition & 1 deletion cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S
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@@ -1,4 +1,4 @@
#Copyright 202[x] Silicon Labs, Inc.
#Copyright (c) 2024 Dolphin Design
#
#This file, and derivatives thereof are licensed under the
#Solderpad License, Version 2.0 (the "License");
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66 changes: 66 additions & 0 deletions cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S
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Expand Up @@ -1511,6 +1511,72 @@ _jrsw31:fsw f31, -8(x31)
cv.lbu x31, (x1), 4
fcvt.s.wu f31, x31

# 20
auipc x0, 0x40000
flw f0, 0(x0)
auipc x1, 0x40000
flw f1, 0(x1)
auipc x2, 0x40000
flw f2, 0(x2)
auipc x3, 0x40000
flw f3, 0(x3)
auipc x4, 0x40000
flw f4, 0(x4)
auipc x5, 0x40000
flw f5, 0(x5)
auipc x6, 0x40000
flw f6, 0(x6)
auipc x7, 0x40000
flw f7, 0(x7)
auipc x8, 0x40000
flw f8, 0(x8)
auipc x9, 0x40000
flw f9, 0(x9)
auipc x10, 0x40000
flw f10, 0(x10)
auipc x11, 0x40000
flw f11, 0(x11)
auipc x12, 0x40000
flw f12, 0(x12)
auipc x13, 0x40000
flw f13, 0(x13)
auipc x14, 0x40000
flw f14, 0(x14)
auipc x15, 0x40000
flw f15, 0(x15)
auipc x16, 0x40000
flw f16, 0(x16)
auipc x17, 0x40000
flw f17, 0(x17)
auipc x18, 0x40000
flw f18, 0(x18)
auipc x19, 0x40000
flw f19, 0(x19)
auipc x20, 0x40000
flw f20, 0(x20)
auipc x21, 0x40000
flw f21, 0(x21)
auipc x22, 0x40000
flw f22, 0(x22)
auipc x23, 0x40000
flw f23, 0(x23)
auipc x24, 0x40000
flw f24, 0(x24)
auipc x25, 0x40000
flw f25, 0(x25)
auipc x26, 0x40000
flw f26, 0(x26)
auipc x27, 0x40000
flw f27, 0(x27)
auipc x28, 0x40000
flw f28, 0(x28)
auipc x29, 0x40000
flw f29, 0(x29)
auipc x30, 0x40000
flw f30, 0(x30)
auipc x31, 0x40000
flw f31, 0(x31)

# for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end
######### FOR PULP_FPU CFG - END #########

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