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Rework PCI emulation to better expose inner data #57

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Rework PCI emulation to better expose inner data #57

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4ee6fae
Rework PCI emulation to better expose inner data
pfmooney Oct 6, 2021
3082289
CR feedback, round 1
pfmooney Oct 18, 2021
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7 changes: 6 additions & 1 deletion propolis/src/block/file.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,7 @@ impl Driver {
})
}
fn blocking_loop(&self, sctx: &mut SyncCtx) {
let mut idled = false;
loop {
if sctx.check_yield() {
break;
Expand All @@ -113,14 +114,18 @@ impl Driver {
let mut guard = self.queue.lock().unwrap();
if let Some(req) = guard.pop_front() {
drop(guard);
idled = false;
let ctx = sctx.dispctx();
match process_request(&self.fp, &req, &ctx) {
Ok(_) => req.complete(block::Result::Success, &ctx),
Err(_) => req.complete(block::Result::Failure, &ctx),
}
} else {
// wait until more requests are available
self.idle_threads.add_permits(1);
if !idled {
self.idle_threads.add_permits(1);
idled = true;
}
let _guard = self
.cv
.wait_while(guard, |g| {
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