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    • Verilog Ethernet components for FPGA implementation
      Verilog
      MIT License
      716000Updated Jan 3, 2025Jan 3, 2025
    • Verilog AXI stream components for FPGA implementation
      Python
      MIT License
      233000Updated Aug 7, 2024Aug 7, 2024
    • Verilog I2C interface for FPGA implementation
      Verilog
      MIT License
      176000Updated Jul 15, 2024Jul 15, 2024
    • Verilog PCI express components
      Verilog
      MIT License
      312000Updated Apr 26, 2024Apr 26, 2024
    • An io_uring backed runtime for Rust
      Rust
      MIT License
      128002Updated Mar 19, 2024Mar 19, 2024
    • io-uring

      Public
      The `io_uring` library for Rust
      Rust
      Apache License 2.0
      139000Updated Feb 8, 2024Feb 8, 2024
    • PCI express simulation framework for Cocotb
      Python
      MIT License
      49000Updated Nov 28, 2023Nov 28, 2023
    • Ethernet interface modules for Cocotb
      Python
      MIT License
      19000Updated Nov 7, 2023Nov 7, 2023
    • Rust
      MIT License
      2000Updated Jul 14, 2022Jul 14, 2022