Add BTI landing pads to the AArch64 SHA2 assembly

The Arm Branch Target Identification (BTI) extension guards against branching to an unintended instruction. To support BTI add the landing pad instructions to the SHA2 functions. These are from the hint space so are a nop on hardware that lacks BTI support or if BTI isn't enabled. Reviewed-by: Allan Jude <[email protected]> Reviewed-by: Brian Behlendorf <[email protected]> Reviewed-by: Tino Reichardt <[email protected]> Signed-off-by: Andrew Turner <[email protected]> Closes #14862 Closes #15339
openzfs · Oct 3, 2023 · f795e90 · f795e90
1 parent eb955f6
commit f795e90
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diff --git a/module/icp/asm-aarch64/sha2/sha256-armv8.S b/module/icp/asm-aarch64/sha2/sha256-armv8.S
@@ -49,6 +49,7 @@
 .type	zfs_sha256_block_armv7,%function
 .align	6
 zfs_sha256_block_armv7:
+	hint	#34					// bti c
 	stp	x29,x30,[sp,#-128]!
 	add	x29,sp,#0
 
@@ -1015,6 +1016,7 @@ zfs_sha256_block_armv7:
 .type	zfs_sha256_block_armv8,%function
 .align	6
 zfs_sha256_block_armv8:
+	hint		#34				// bti c
 .Lv8_entry:
 	stp		x29,x30,[sp,#-16]!
 	add		x29,sp,#0
@@ -1155,6 +1157,7 @@ zfs_sha256_block_armv8:
 .type	zfs_sha256_block_neon,%function
 .align	4
 zfs_sha256_block_neon:
+	hint	#34					// bti c
 .Lneon_entry:
 	stp	x29, x30, [sp, #-16]!
 	mov	x29, sp

diff --git a/module/icp/asm-aarch64/sha2/sha512-armv8.S b/module/icp/asm-aarch64/sha2/sha512-armv8.S
@@ -73,6 +73,7 @@
 .type	zfs_sha512_block_armv7,%function
 .align	6
 zfs_sha512_block_armv7:
+	hint	#34					// bti c
 	stp	x29,x30,[sp,#-128]!
 	add	x29,sp,#0
 
@@ -1040,6 +1041,7 @@ zfs_sha512_block_armv7:
 .type	zfs_sha512_block_armv8,%function
 .align	6
 zfs_sha512_block_armv8:
+	hint		#34				// bti c
 .Lv8_entry:
 	// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later
 	stp		x29,x30,[sp,#-16]!