Review comments 3

src/common/snippets/include/snippets/lowered/expression.hpp

@@ -132,7 +132,7 @@ class Expression : public std::enable_shared_from_this<Expression> {
     //   2. This number can be changed and updated during whole pipeline, so its absolute values are meaningless.
     //   3. This number can be negative, positive and zero.
     double m_exec_num = 0;
-    std::set<Reg> m_live_regs;
+    std::set<Reg> m_live_regs{};
 };
 
 } // namespace lowered

src/common/snippets/include/snippets/lowered/pass/init_registers.hpp

@@ -0,0 +1,36 @@
+// Copyright (C) 2025 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#pragma once
+
+#include "pass.hpp"
+#include "snippets/generator.hpp"
+#include "snippets/lowered/reg_manager.hpp"
+
+namespace ov {
+namespace snippets {
+namespace lowered {
+namespace pass {
+
+/**
+ * @interface InitRegisters
+ * @brief This pass combines all register-related transformations that are needed to initialize register info.
+ * @ingroup snippets
+ */
+class InitRegisters : public Pass {
+public:
+    OPENVINO_RTTI("InitRegisters", "0", Pass)
+    InitRegisters(const std::shared_ptr<const Generator>& generator,
+                  const std::shared_ptr<PassConfig>& pass_config);
+    bool run(LinearIR& linear_ir) override;
+
+private:
+    lowered::RegManager m_reg_manager;
+    const std::shared_ptr<PassConfig>& m_pass_config;
+};
+
+} // namespace pass
+} // namespace lowered
+} // namespace snippets
+} // namespace ov

src/common/snippets/src/lowered/pass/assign_registers.cpp

@@ -45,9 +45,9 @@ AssignRegisters::RegMap AssignRegisters::assign_regs_manually(const LinearIR& li
             manually_assigned[out_reg] = assigned;
             // Buffer abstract registers validation:
             bool all_equal = true;
-            for (const auto& pd : expr->get_input_port_descriptors())
+            for (const auto& pd : buffer->get_input_port_descriptors())
                 all_equal &= pd->get_reg() == out_reg;
-            for (const auto& pd : expr->get_output_port_descriptors())
+            for (const auto& pd : buffer->get_output_port_descriptors())
                 all_equal &= pd->get_reg() == out_reg;
             OPENVINO_ASSERT(all_equal, "Buffer must have same register on all inputs and outputs");
         } else if (ov::is_type<op::HorizonMax>(op) || ov::is_type<op::HorizonSum>(op)) {
@@ -109,7 +109,7 @@ bool AssignRegisters::run(LinearIR& linear_ir) {
         }
     };
 
-    // A variable live LiveInterval - is a range (start, stop) of op indexes, such that
+    // A variable LiveInterval - is a range (start, stop) of op indexes, such that
     // the variable is alive within this range (defined but not used by the last user)
     std::map<LiveInterval, Reg, by_starting> live_intervals_vec, live_intervals_gpr;
     for (const auto& regint : m_reg_manager.get_live_range_map()) {

src/common/snippets/src/lowered/pass/init_live_ranges.cpp

@@ -36,7 +36,8 @@ bool InitLiveRanges::run(LinearIR& linear_ir) {
         const auto& expr = *expr_it;
         const auto op = expr->get_node();
         if (pass_through_expr(expr)) {
-            expr->set_live_regs(std::prev(expr_it)->get()->get_live_regs());
+            if(expr_it != linear_ir.begin())
+                expr->set_live_regs(std::prev(expr_it)->get()->get_live_regs());
             continue;
         }
         const double start = expr->get_exec_num();
@@ -66,6 +67,8 @@ bool InitLiveRanges::run(LinearIR& linear_ir) {
                     consumer.get_descriptor_ptr()->set_reg(reg);
                     const auto& consumer_expr = consumer.get_expr();
                     stop = std::max(stop, consumer_expr->get_exec_num());
+                    // Note: pass_through expression don't affect registers' life times,
+                    // so we should examine their consumers to understand when the register will actually be used
                     if (pass_through_expr(consumer_expr)) {
                         for (const auto& connector : consumer_expr->get_output_port_connectors())
                             to_visit.push(connector);

src/common/snippets/src/lowered/pass/init_registers.cpp

@@ -0,0 +1,35 @@
+// Copyright (C) 2024 Intel Corporation
+// SPDX-License-Identifier: Apache-2.0
+//
+
+#include "snippets/lowered/pass/init_registers.hpp"
+#include "snippets/lowered/pass/init_live_ranges.hpp"
+#include "snippets/lowered/pass/assign_registers.hpp"
+#include "snippets/lowered/pass/insert_reg_spills.hpp"
+#include "snippets/itt.hpp"
+
+namespace ov {
+namespace snippets {
+namespace lowered {
+namespace pass {
+
+InitRegisters::InitRegisters(const std::shared_ptr<const Generator>& generator,
+                             const std::shared_ptr<PassConfig>& pass_config) :
+                             Pass(), m_reg_manager(generator), m_pass_config(pass_config) {
+}
+
+bool InitRegisters::run(LinearIR& linear_ir) {
+    OV_ITT_SCOPED_TASK(ov::pass::itt::domains::SnippetsTransform, "Snippets::InitRegisters");
+    lowered::pass::PassPipeline reg_pipeline(m_pass_config);
+    reg_pipeline.register_pass<lowered::pass::InitLiveRanges>(m_reg_manager);
+    reg_pipeline.register_pass<lowered::pass::AssignRegisters>(m_reg_manager);
+    reg_pipeline.register_pass<lowered::pass::InsertRegSpills>(m_reg_manager);
+    reg_pipeline.run(linear_ir);
+    return true;
+}
+
+} // namespace pass
+} // namespace lowered
+} // namespace snippets
+} // namespace ov
+

src/common/snippets/src/lowered/pass/validate.cpp

@@ -103,7 +103,7 @@ void validate_loop_end(const ExpressionPtr& expr, const LinearIR& linear_ir) {
     const auto num_inputs = expr->get_input_count();
     OPENVINO_ASSERT(num_inputs >= 1, "LoopEnd expression must have at least 1 input");
     OPENVINO_ASSERT(expr->get_input_port_connector(num_inputs - 1)->get_source().get_expr()->get_node() == loop_begin,
-                    "LopEnd expression must have LoopBegin attached to the last connector");
+                    "LoopEnd expression must have LoopBegin attached to the last connector");
 
     const auto& loop_manager = linear_ir.get_loop_manager();
     const auto& loop_info = loop_manager->get_loop_info<UnifiedLoopInfo>(loop_end->get_id());

src/common/snippets/src/op/subgraph.cpp

@@ -26,7 +26,6 @@
 #include "snippets/lowered/port_descriptor.hpp"
 #include "snippets/lowered/linear_ir.hpp"
 #include "snippets/lowered/linear_ir_builder.hpp"
-#include "snippets/lowered/pass/assign_registers.hpp"
 #include "snippets/lowered/pass/mark_loops.hpp"
 #include "snippets/lowered/pass/split_loops.hpp"
 #include "snippets/lowered/pass/fuse_loops.hpp"
@@ -56,10 +55,7 @@
 #include "snippets/lowered/pass/set_load_store_scalar.hpp"
 #include "snippets/lowered/pass/extract_loop_invariants.hpp"
 
-#include "snippets/lowered/reg_manager.hpp"
-#include "snippets/lowered/pass/assign_registers.hpp"
-#include "snippets/lowered/pass/init_live_ranges.hpp"
-#include "snippets/lowered/pass/insert_reg_spills.hpp"
+#include "snippets/lowered/pass/init_registers.hpp"
 
 #include "transformations/utils/utils.hpp"
 
@@ -510,10 +506,7 @@ void Subgraph::control_flow_transformations(size_t min_parallel_work_amount, siz
     //    3. OptimizeLoopSingleEvaluation must be called after CleanupLoopOffsets
     //       since CleanupLoopOffsets can't handle loops with evaluate_once = true
 
-    lowered::RegManager reg_manager(get_generator());
-    gen_pipeline.register_pass<lowered::pass::InitLiveRanges>(reg_manager);
-    gen_pipeline.register_pass<lowered::pass::AssignRegisters>(reg_manager);
-    gen_pipeline.register_pass<lowered::pass::InsertRegSpills>(reg_manager);
+    gen_pipeline.register_pass<lowered::pass::InitRegisters>(get_generator(), lowered_pass_config);
     gen_pipeline.register_pass<lowered::pass::InsertSpecificIterations>();
     gen_pipeline.register_pass<lowered::pass::NormalizeLoopIDs>();
     gen_pipeline.register_pass<lowered::pass::ValidateExpandedLoops>();

src/plugins/intel_cpu/src/emitters/snippets/x64/jit_kernel_emitter.cpp

@@ -106,7 +106,7 @@ void jit_kernel_emitter::emit_impl(const std::vector<size_t>& in, const std::vec
         case emitter_in_out_map::vec_to_vec:
             return {snippets::RegType::vec, snippets::RegType::vec};
         default:
-            OV_CPU_JIT_EMITTER_THROW("Unsupported emitter_in_ou_map instance");
+            OV_CPU_JIT_EMITTER_THROW("Unsupported emitter_in_out_map instance");
         }
     };
     std::vector<Xbyak::Reg64> aux_tmp_regs{};

src/plugins/intel_cpu/src/emitters/snippets/x64/jit_reg_spill_emitters.cpp

@@ -5,9 +5,6 @@
 #include "jit_reg_spill_emitters.hpp"
 
 #include "emitters/plugin/x64/utils.hpp"
-#include "emitters/snippets/jit_snippets_call_args.hpp"
-#include "emitters/snippets/x64/utils.hpp"
-#include "snippets/utils/utils.hpp"
 
 using namespace Xbyak;
 using namespace dnnl::impl;