Initial draft of PC for Verilator modeling for software. #694
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Project-Descriptions-and-Plans/Verilator-models-for-software/ * images/avr-studio.png: Created. * verilator-models-for-software-pc.md: Created. Signed-off-by: Jeremy Bennett <[email protected]>
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Please add a license header for this file. The SPDX two-liner is sufficient:
<!---
Copyright 2024 Embecosm, OpenHW Group
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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davideschiavone
requested changes
Sep 10, 2024
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| From the [Verilator Wikipedia entry](https://www.veripool.org/wiki/verilator): | ||
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| > Verilator is a free and open-source software tool capable of converting Synthesizable Verilog/SystemVerilog to a cycle-accurate cycle-accurate, 2-state behavioral model in C++ or SystemC. |
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cycle-accurate is written twice
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Project-Descriptions-and-Plans/Verilator-models-for-software/