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In case, the f6(rs2) register is infinity and the f5(rs1) register is any number, the result from spike(ISS) is the XOR of a sign of f6 (i.e. positive) with the sign bit of f5(rs1) register for FSGNJX.S instruction but the result from FPU is a NaN which is incorrect.
References
Screenshots of logs from the spike and FPU design are attached below for a reference
The text was updated successfully, but these errors were encountered:
AuringzaibSabir
changed the title
fsgnjx.s instruction is misbehaving with infinity as operand-bfsgnjx.s instruction is misbehaving with operand-b as infinity
Oct 11, 2022
Found a bug in a floating point unit.
fsgnjx.s
instruction is misbehaving.Ideally
fsgnjx.s
copy a signed value from one register to another register, while modifying the sign bit based on the sign from another value.Examples:
In case, the
f6
(rs2) register is infinity and thef5
(rs1) register is any number, the result from spike(ISS) is the XOR of a sign of f6 (i.e. positive) with the sign bit off5
(rs1) register forFSGNJX.S
instruction but the result from FPU is aNaN
which is incorrect.References
Screenshots of logs from the spike and FPU design are attached below for a reference
The text was updated successfully, but these errors were encountered: