Mmu unify - task 1

[AngelaGonzalezMarino]

Merge of sv32 and sv39 MMUs.
Parametrization strategy followed for new parameters.

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Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/mmu_unify/cva6_mmu.sv|605|
core/mmu_unify/cva6_mmu.sv|626|
core/mmu_unify/cva6_ptw.sv|37|
core/mmu_unify/cva6_ptw.sv|102|
core/mmu_unify/cva6_ptw.sv|113|
core/mmu_unify/cva6_ptw.sv|139|
core/mmu_unify/cva6_ptw.sv|143|
core/mmu_unify/cva6_ptw.sv|146|
core/mmu_unify/cva6_ptw.sv|151|
core/mmu_unify/cva6_ptw.sv|156|
core/mmu_unify/cva6_ptw.sv|189|
core/mmu_unify/cva6_ptw.sv|247|
core/mmu_unify/cva6_ptw.sv|328|
core/mmu_unify/cva6_ptw.sv|392|
core/mmu_unify/cva6_shared_tlb.sv|167|
core/mmu_unify/cva6_tlb.sv|204|
core/mmu_unify/cva6_tlb.sv|247|

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Suggested change

	import ariane_pkg::*;
	import ariane_pkg::*;

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Suggested change

	parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
	parameter int unsigned INSTR_TLB_ENTRIES = 4,
	parameter int unsigned DATA_TLB_ENTRIES = 4,
	parameter int unsigned ASID_WIDTH = 1,
	parameter int unsigned ASID_LEN = 1,
	parameter int unsigned VPN_LEN = 1,
	parameter int unsigned PT_LEVELS = 1
	parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
	parameter int unsigned INSTR_TLB_ENTRIES = 4,
	parameter int unsigned DATA_TLB_ENTRIES = 4,
	parameter int unsigned ASID_WIDTH = 1,
	parameter int unsigned ASID_LEN = 1,
	parameter int unsigned VPN_LEN = 1,
	parameter int unsigned PT_LEVELS = 1

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	input logic clk_i,
	input logic rst_ni,
	input logic flush_i,
	input logic enable_translation_i,
	input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
	// IF interface
	input icache_arsp_t icache_areq_i,
	output icache_areq_t icache_areq_o,
	// LSU interface
	// this is a more minimalistic interface because the actual addressing logic is handled
	// in the LSU as we distinguish load and stores, what we do here is simple address translation
	input exception_t misaligned_ex_i,
	input logic lsu_req_i, // request address translation
	input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in
	input logic lsu_is_store_i, // the translation is requested by a store
	// if we need to walk the page table we can't grant in the same cycle
	// Cycle 0
	output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
	output logic [riscv::PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit)
	// Cycle 1
	output logic lsu_valid_o, // translation is valid
	output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address
	output exception_t lsu_exception_o, // address translation threw an exception
	// General control signals
	input riscv::priv_lvl_t priv_lvl_i,
	input riscv::priv_lvl_t ld_st_priv_lvl_i,
	input logic sum_i,
	input logic mxr_i,
	// input logic flag_mprv_i,
	input logic [riscv::PPNW-1:0] satp_ppn_i,
	input logic [ASID_WIDTH-1:0] asid_i,
	input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
	input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
	input logic flush_tlb_i,
	// Performance counters
	output logic itlb_miss_o,
	output logic dtlb_miss_o,
	// PTW memory interface
	input dcache_req_o_t req_port_i,
	output dcache_req_i_t req_port_o,
	// PMP
	input riscv::pmpcfg_t [15:0] pmpcfg_i,
	input logic [15:0][riscv::PLEN-3:0] pmpaddr_i
	);
	// memory management, pte for cva6
	localparam type pte_cva6_t = struct packed {
	// typedef struct packed {
	logic [riscv::PPNW-1:0] ppn; // PPN length for
	logic [1:0] rsw;
	logic d;
	logic a;
	logic g;
	logic u;
	logic x;
	logic w;
	logic r;
	logic v;
	} ;
	localparam type tlb_update_cva6_t = struct packed {
	// typedef struct packed {
	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;
	} ;
	logic iaccess_err; // insufficient privilege to access this instruction page
	logic daccess_err; // insufficient privilege to access this data page
	logic ptw_active; // PTW is currently walking a page table
	logic walking_instr; // PTW is walking because of an ITLB miss
	logic ptw_error; // PTW threw an exception
	logic ptw_access_exception; // PTW threw an access exception (PMPs)
	logic [riscv::PLEN-1:0] ptw_bad_paddr; // PTW PMP exception bad physical addr
	logic [riscv::VLEN-1:0] update_vaddr;
	// tlb_update_t update_ptw_itlb, update_ptw_dtlb;
	tlb_update_cva6_t update_itlb, update_dtlb, update_shared_tlb;
	logic itlb_lu_access;
	pte_cva6_t itlb_content;
	logic [PT_LEVELS-2:0] itlb_is_page;
	logic itlb_lu_hit;
	logic dtlb_lu_access;
	pte_cva6_t dtlb_content;
	logic [PT_LEVELS-2:0] dtlb_is_page;
	logic dtlb_lu_hit;
	logic shared_tlb_access;
	logic [riscv::VLEN-1:0] shared_tlb_vaddr;
	logic shared_tlb_hit;
	logic itlb_req;
	// Assignments
	assign itlb_lu_access = icache_areq_i.fetch_req;
	assign dtlb_lu_access = lsu_req_i;
	cva6_tlb #(
	.CVA6Cfg (CVA6Cfg),
	.TLB_ENTRIES(INSTR_TLB_ENTRIES),
	.ASID_WIDTH (ASID_WIDTH),
	.ASID_LEN (ASID_LEN),
	.VPN_LEN(VPN_LEN),
	.PT_LEVELS(PT_LEVELS),
	.pte_cva6_t(pte_cva6_t),
	.tlb_update_cva6_t(tlb_update_cva6_t)
	) i_itlb (
	.clk_i (clk_i),
	.rst_ni (rst_ni),
	.flush_i(flush_tlb_i),
	.update_i(update_itlb),
	.lu_access_i (itlb_lu_access),
	.lu_asid_i (asid_i),
	.asid_to_be_flushed_i (asid_to_be_flushed_i),
	.vaddr_to_be_flushed_i(vaddr_to_be_flushed_i),
	.lu_vaddr_i (icache_areq_i.fetch_vaddr),
	.lu_content_o (itlb_content),
	.lu_is_page_o(itlb_is_page),
	.lu_hit_o (itlb_lu_hit)
	);
	cva6_tlb #(
	.CVA6Cfg (CVA6Cfg),
	.TLB_ENTRIES(DATA_TLB_ENTRIES),
	.ASID_WIDTH (ASID_WIDTH),
	.ASID_LEN (ASID_LEN),
	.VPN_LEN(VPN_LEN),
	.PT_LEVELS(PT_LEVELS),
	.pte_cva6_t(pte_cva6_t),
	.tlb_update_cva6_t(tlb_update_cva6_t)
	) i_dtlb (
	.clk_i (clk_i),
	.rst_ni (rst_ni),
	.flush_i(flush_tlb_i),
	.update_i(update_dtlb),
	.lu_access_i (dtlb_lu_access),
	.lu_asid_i (asid_i),
	.asid_to_be_flushed_i (asid_to_be_flushed_i),
	.vaddr_to_be_flushed_i(vaddr_to_be_flushed_i),
	.lu_vaddr_i (lsu_vaddr_i),
	.lu_content_o (dtlb_content),
	.lu_is_page_o(dtlb_is_page),
	.lu_hit_o (dtlb_lu_hit)
	);
	cva6_shared_tlb #(
	.CVA6Cfg (CVA6Cfg),
	.SHARED_TLB_DEPTH(64),
	.SHARED_TLB_WAYS (2),
	.ASID_WIDTH (ASID_WIDTH),
	.ASID_LEN (ASID_LEN),
	.VPN_LEN(VPN_LEN),
	.PT_LEVELS(PT_LEVELS),
	.pte_cva6_t(pte_cva6_t),
	.tlb_update_cva6_t(tlb_update_cva6_t)
	) i_shared_tlb (
	.clk_i (clk_i),
	.rst_ni (rst_ni),
	.flush_i(flush_tlb_i),
	.enable_translation_i (enable_translation_i),
	.en_ld_st_translation_i(en_ld_st_translation_i),
	.asid_i (asid_i),
	// from TLBs
	// did we miss?
	.itlb_access_i(itlb_lu_access),
	.itlb_hit_i (itlb_lu_hit),
	.itlb_vaddr_i (icache_areq_i.fetch_vaddr),
	.dtlb_access_i(dtlb_lu_access),
	.dtlb_hit_i (dtlb_lu_hit),
	.dtlb_vaddr_i (lsu_vaddr_i),
	// to TLBs, update logic
	.itlb_update_o(update_itlb),
	.dtlb_update_o(update_dtlb),
	input logic clk_i,
	input logic rst_ni,
	input logic flush_i,
	input logic enable_translation_i,
	input logic en_ld_st_translation_i, // enable virtual memory translation for load/stores
	// IF interface
	input icache_arsp_t icache_areq_i,
	output icache_areq_t icache_areq_o,
	// LSU interface
	// this is a more minimalistic interface because the actual addressing logic is handled
	// in the LSU as we distinguish load and stores, what we do here is simple address translation
	input exception_t misaligned_ex_i,
	input logic lsu_req_i, // request address translation
	input logic [riscv::VLEN-1:0] lsu_vaddr_i, // virtual address in
	input logic lsu_is_store_i, // the translation is requested by a store
	// if we need to walk the page table we can't grant in the same cycle
	// Cycle 0
	output logic lsu_dtlb_hit_o, // sent in the same cycle as the request if translation hits in the DTLB
	output logic [riscv::PPNW-1:0] lsu_dtlb_ppn_o, // ppn (send same cycle as hit)
	// Cycle 1
	output logic lsu_valid_o, // translation is valid
	output logic [riscv::PLEN-1:0] lsu_paddr_o, // translated address
	output exception_t lsu_exception_o, // address translation threw an exception
	// General control signals
	input riscv::priv_lvl_t priv_lvl_i,
	input riscv::priv_lvl_t ld_st_priv_lvl_i,
	input logic sum_i,
	input logic mxr_i,
	// input logic flag_mprv_i,
	input logic [riscv::PPNW-1:0] satp_ppn_i,
	input logic [ASID_WIDTH-1:0] asid_i,
	input logic [ASID_WIDTH-1:0] asid_to_be_flushed_i,
	input logic [riscv::VLEN-1:0] vaddr_to_be_flushed_i,
	input logic flush_tlb_i,

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	.itlb_miss_o(itlb_miss_o),
	.dtlb_miss_o(dtlb_miss_o),
	.shared_tlb_access_o(shared_tlb_access),
	.shared_tlb_hit_o (shared_tlb_hit),
	.shared_tlb_vaddr_o (shared_tlb_vaddr),
	.itlb_req_o (itlb_req),
	// to update shared tlb
	.shared_tlb_update_i(update_shared_tlb)
	);
	cva6_ptw #(
	.CVA6Cfg (CVA6Cfg),
	.ASID_WIDTH(ASID_WIDTH),
	.VPN_LEN(VPN_LEN),
	.PT_LEVELS(PT_LEVELS),
	.pte_cva6_t(pte_cva6_t),
	.tlb_update_cva6_t(tlb_update_cva6_t)
	) i_ptw (
	.clk_i (clk_i),
	.rst_ni (rst_ni),
	.flush_i(flush_i),
	.ptw_active_o (ptw_active),
	.walking_instr_o (walking_instr),
	.ptw_error_o (ptw_error),
	.ptw_access_exception_o(ptw_access_exception),
	.lsu_is_store_i(lsu_is_store_i),
	output logic itlb_miss_o,
	output logic dtlb_miss_o,

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	.req_port_i (req_port_i),
	.req_port_o (req_port_o),
	// to Shared TLB, update logic
	.shared_tlb_update_o(update_shared_tlb),
	.update_vaddr_o(update_vaddr),
	.asid_i(asid_i),
	// from shared TLB
	// did we miss?
	.shared_tlb_access_i(shared_tlb_access),
	.shared_tlb_hit_i (shared_tlb_hit),
	.shared_tlb_vaddr_i (shared_tlb_vaddr),
	.itlb_req_i(itlb_req),
	// from CSR file
	.satp_ppn_i(satp_ppn_i), // ppn from satp
	.mxr_i (mxr_i),
	// Performance counters
	.shared_tlb_miss_o(), //open for now
	input dcache_req_o_t req_port_i,
	output dcache_req_i_t req_port_o,

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	lsu_exception_o = {
	// check for sufficient access privileges - throw a page fault if necessary
	if (daccess_err) begin
	lsu_exception_o = {
	riscv::LOAD_PAGE_FAULT,
	{{riscv::XLEN - riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}}, lsu_vaddr_q},
	1'b1
	};
	// Check if any PMPs are violated
	end else if (!pmp_data_allow) begin
	lsu_exception_o = {
	riscv::LD_ACCESS_FAULT,
	lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN>riscv::VLEN)?(riscv::PLEN-riscv::VLEN) : 0],
	1'b1
	};
	end
	end
	end else
	// ---------
	// DTLB Miss
	// ---------
	// watch out for exceptions
	if (ptw_active && !walking_instr) begin
	// page table walker threw an exception
	if (ptw_error) begin
	// an error makes the translation valid
	lsu_valid_o = 1'b1;
	// the page table walker can only throw page faults
	if (lsu_is_store_q) begin
	lsu_exception_o = {
	riscv::STORE_PAGE_FAULT,
	{{riscv::XLEN - riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}}, update_vaddr},
	1'b1
	};
	end else begin
	lsu_exception_o = {
	riscv::LOAD_PAGE_FAULT,
	{{riscv::XLEN - riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}}, update_vaddr},
	1'b1
	};
	end
	end
	if (ptw_access_exception) begin
	// an error makes the translation valid
	lsu_valid_o = 1'b1;
	// Any fault of the page table walk should be based of the original access type
	lsu_exception_o = {

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	riscv::LOAD_PAGE_FAULT,
	{{riscv::XLEN - riscv::VLEN{lsu_vaddr_q[riscv::VLEN-1]}}, update_vaddr},
	riscv::LD_ACCESS_FAULT,
	ptw_bad_paddr[riscv::PLEN-1:(riscv::PLEN>riscv::VLEN)?(riscv::PLEN-riscv::VLEN) : 0],

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	if (ptw_access_exception) begin
	// an error makes the translation valid
	lsu_valid_o = 1'b1;
	// Any fault of the page table walk should be based of the original access type
	lsu_exception_o = {riscv::LD_ACCESS_FAULT, ptw_bad_paddr[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0], 1'b1};
	end
	end
	end // If translation is not enabled, check the paddr immediately against PMPs
	end // If translation is not enabled, check the paddr immediately against PMPs

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	if (lsu_is_store_q) begin
	lsu_exception_o = {riscv::ST_ACCESS_FAULT, lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0], 1'b1};
	end else begin
	lsu_exception_o = {riscv::LD_ACCESS_FAULT, lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0], 1'b1};
	if (lsu_is_store_q) begin
	lsu_exception_o = {
	riscv::ST_ACCESS_FAULT,
	lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN>riscv::VLEN)?(riscv::PLEN-riscv::VLEN) : 0],
	1'b1
	};
	end else begin
	lsu_exception_o = {
	riscv::LD_ACCESS_FAULT,
	lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN>riscv::VLEN)?(riscv::PLEN-riscv::VLEN) : 0],
	1'b1
	};
	end

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	end
	// Load/store PMP check
	pmp #(
	.CVA6Cfg (CVA6Cfg),
	.PLEN (riscv::PLEN),
	.PMP_LEN (riscv::PLEN - 2),
	.NR_ENTRIES(CVA6Cfg.NrPMPEntries)
	) i_pmp_data (
	.addr_i (lsu_paddr_o),
	.priv_lvl_i (ld_st_priv_lvl_i),
	.access_type_i(pmp_access_type),
	// Configuration
	.conf_addr_i (pmpaddr_i),
	.conf_i (pmpcfg_i),
	.allow_o (pmp_data_allow)
	);

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Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/mmu_unify/cva6_mmu.sv|541|
core/mmu_unify/cva6_mmu.sv|576|
core/mmu_unify/cva6_mmu.sv|582|
core/mmu_unify/cva6_mmu.sv|584|
core/mmu_unify/cva6_mmu.sv|627|
core/mmu_unify/cva6_ptw.sv|37|
core/mmu_unify/cva6_ptw.sv|102|
core/mmu_unify/cva6_ptw.sv|113|
core/mmu_unify/cva6_ptw.sv|139|
core/mmu_unify/cva6_ptw.sv|143|
core/mmu_unify/cva6_ptw.sv|146|
core/mmu_unify/cva6_ptw.sv|151|
core/mmu_unify/cva6_ptw.sv|156|
core/mmu_unify/cva6_ptw.sv|189|
core/mmu_unify/cva6_ptw.sv|247|
core/mmu_unify/cva6_ptw.sv|328|
core/mmu_unify/cva6_ptw.sv|392|
core/mmu_unify/cva6_shared_tlb.sv|167|
core/mmu_unify/cva6_tlb.sv|204|
core/mmu_unify/cva6_tlb.sv|247|

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	);
	);

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	// memory management, pte for cva6
	// memory management, pte for cva6

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	// typedef struct packed {
	logic [riscv::PPNW-1:0] ppn; // PPN length for
	logic [1:0] rsw;
	// typedef struct packed {
	logic [riscv::PPNW-1:0] ppn; // PPN length for
	logic [1:0] rsw;

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	} ;
	};

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[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	// typedef struct packed {
	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;
	} ;
	// typedef struct packed {
	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;
	};

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	generate
	for (i=0; i < PT_LEVELS-1; i++) begin
	assign lsu_paddr_o [PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] = //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]==0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];
	assign lsu_dtlb_ppn_o[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] = //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]==0)) ? //
	dtlb_content.ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]!=0)?
	generate
	for (i = 0; i < PT_LEVELS - 1; i++) begin
	assign lsu_paddr_o [PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] = //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];
	assign lsu_dtlb_ppn_o[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] = //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_content.ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]!=0)?

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	(VPN_LEN/PT_LEVELS)'(lsu_vaddr_n[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN -1 : (24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-1) ) -1): (riscv::PLEN > riscv::VLEN) ? 24 :24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-2)]));
	end
	if(riscv::IS_XLEN64) begin
	assign lsu_dtlb_ppn_o[riscv::PPNW-1:PPNWMin+1] = (en_ld_st_translation_i && !misaligned_ex_q.valid) ?
	(VPN_LEN/PT_LEVELS)'(lsu_vaddr_n[((riscv::PLEN > riscv::VLEN) ? riscv::VLEN -1 : (24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-1) ) -1): (riscv::PLEN > riscv::VLEN) ? 24 :24 + (VPN_LEN/PT_LEVELS)*(PT_LEVELS-i-2)]));
	end
	if (riscv::IS_XLEN64) begin
	assign lsu_dtlb_ppn_o[riscv::PPNW-1:PPNWMin+1] = (en_ld_st_translation_i && !misaligned_ex_q.valid) ?

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	end
	end

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	endgenerate
	endgenerate

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	riscv::ST_ACCESS_FAULT, riscv::XLEN'(lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0]), 1'b1
	riscv::ST_ACCESS_FAULT,
	riscv::XLEN'(lsu_paddr_o[riscv::PLEN-1:(riscv::PLEN > riscv::VLEN) ? (riscv::PLEN - riscv::VLEN) : 0]),
	1'b1

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic [riscv::PPNW-1:0] ppn; // PPN length for
	logic [1:0] rsw;
	logic [riscv::PPNW-1:0] ppn; // PPN length for
	logic [1:0] rsw;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;
	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	for (i=0; i < PT_LEVELS-1; i++) begin
	for (i = 0; i < PT_LEVELS - 1; i++) begin

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]==0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]==0)) ? //
	dtlb_content.ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]!=0)?
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_content.ppn[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1] : //
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0]!=0)?

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	// pointer to next level of page table
	if (ptw_lvl_q == PT_LEVELS-1) begin
	// Should already be the last level page table => Error
	ptw_lvl_n = PT_LEVELS-1;
	state_d = PROPAGATE_ERROR;
	end
	else begin
	// if (ptw_lvl_q == 1) begin
	// we are in the second level now
	ptw_lvl_n = ptw_lvl_q+1;
	ptw_pptr_n = {pte.ppn, vaddr_lvl[ptw_lvl_q], (PT_LEVELS)'(0)};
	state_d = WAIT_GRANT;
	// end
	end
	// pointer to next level of page table
	if (ptw_lvl_q == PT_LEVELS - 1) begin
	// Should already be the last level page table => Error
	ptw_lvl_n = PT_LEVELS - 1;
	state_d = PROPAGATE_ERROR;
	end else begin
	// if (ptw_lvl_q == 1) begin
	// we are in the second level now
	ptw_lvl_n = ptw_lvl_q + 1;
	ptw_pptr_n = {pte.ppn, vaddr_lvl[ptw_lvl_q], (PT_LEVELS)'(0)};
	state_d = WAIT_GRANT;
	// end
	end

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	itlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : //
	((en_ld_st_translation_i & dtlb_access_i & ~dtlb_hit_i) ? //
	dtlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : vpn_q[w]);
	itlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : //
	((en_ld_st_translation_i & dtlb_access_i & ~dtlb_hit_i) ? //
	dtlb_vaddr_i[12+((VPN_LEN/PT_LEVELS)*(w+1))-1:12+((VPN_LEN/PT_LEVELS)*w)] : vpn_q[w]);

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	for (int unsigned i = 0; i < TLB_ENTRIES; i++) begin
	// we got a hit so update the pointer as it was least recently used
	for (
	int unsigned i = 0; i < TLB_ENTRIES; i++
	) begin
	// we got a hit so update the pointer as it was least recently used

[github-actions]

✔️ successful run, report available here.

[github-actions]

✔️ successful run, report available here.

[github-actions]

✔️ successful run, report available here.

[github-actions]

✔️ successful run, report available here.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic [1:0] rsw;
	logic [1:0] rsw;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;
	logic valid; // valid flag
	logic [PT_LEVELS-2:0] is_page; //
	logic [VPN_LEN-1:0] vpn; //
	logic [ASID_LEN-1:0] asid; //
	pte_cva6_t content;

[github-actions]

✔️ successful run, report available here.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	for (i = 0; i < PT_LEVELS - 1; i++) begin
	for (i = 0; i < PT_LEVELS - 1; i++) begin

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];
	(en_ld_st_translation_i && !misaligned_ex_q.valid && (|dtlb_is_page_q[i:0] == 0)) ? //
	dtlb_pte_q.ppn [(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i))-1):(riscv::PPNW - (riscv::PLEN - PPNWMin-1)-((VPN_LEN/PT_LEVELS)*(i+1)))] : //
	lsu_vaddr_q[PPNWMin-((VPN_LEN/PT_LEVELS)*(i)):PPNWMin-((VPN_LEN/PT_LEVELS)*(i+1))+1];

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	if (ptw_lvl_q == PT_LEVELS-1) begin
	if (ptw_lvl_q == PT_LEVELS - 1) begin

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	ptw_lvl_n = PT_LEVELS-1;
	ptw_lvl_n = PT_LEVELS - 1;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	end
	else begin
	end else begin

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	ptw_lvl_n = ptw_lvl_q+1;
	ptw_lvl_n = ptw_lvl_q + 1;

[github-actions]

✔️ successful run, report available here.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	generate
	generate