complete tlb merge for sv39x4 v0

openhwgroup · Dec 15, 2023 · 3e7f23f · 3e7f23f
1 parent 478ff59
commit 3e7f23f
Show file tree

Hide file tree

Showing 2 changed files with 10 additions and 6 deletions.
diff --git a/core/include/riscv_pkg.sv b/core/include/riscv_pkg.sv
@@ -39,7 +39,9 @@ package riscv;
   // Warning: VLEN must be superior or equal to PLEN
   localparam VLEN = (XLEN == 32) ? 32 : 64;  // virtual address length
   localparam PLEN = (XLEN == 32) ? 34 : 56;  // physical address length
-
+  localparam GPLEN            = (XLEN == 32) ? 34 : 41; 
+  localparam GPPNW            = (XLEN == 32) ? 22 : 29;
+  localparam GPPN2            = (XLEN == 32) ? riscv::VLEN-33 : 10;
   localparam IS_XLEN32 = (XLEN == 32) ? 1'b1 : 1'b0;
   localparam IS_XLEN64 = (XLEN == 32) ? 1'b0 : 1'b1;
   localparam ModeW = (XLEN == 32) ? 1 : 4;

diff --git a/core/mmu_unify/cva6_mmu.sv b/core/mmu_unify/cva6_mmu.sv
@@ -92,7 +92,7 @@ localparam type pte_cva6_t = struct packed {
 localparam type tlb_update_cva6_t = struct packed {
 // typedef struct packed {
   logic                  valid;      // valid flag
-  logic [HYP_EXT:0][PT_LEVELS-2:0] is_page;      //
+  logic [PT_LEVELS-2:0][HYP_EXT:0] is_page;      //
   logic [VPN_LEN-1:0]    vpn;        //
   logic [HYP_EXT:0][ASID_LEN-1:0]   asid;       //
   pte_cva6_t  [HYP_EXT:0]          content;
@@ -131,11 +131,10 @@ logic                               itlb_req;
 assign itlb_lu_access = icache_areq_i.fetch_req;
 assign dtlb_lu_access = lsu_req_i;
 
-logic [riscv::VLEN-1:0] lu_vaddr_i [HYP_EXT:0];
-assign lu_vaddr_i[0]=icache_areq_i.fetch_vaddr;
 
 cva6_tlb #(
     .CVA6Cfg    (CVA6Cfg),
+    .HYP_EXT(HYP_EXT),
     .TLB_ENTRIES(INSTR_TLB_ENTRIES),
     .ASID_WIDTH (ASID_WIDTH),
     .ASID_LEN (ASID_LEN),
@@ -154,7 +153,8 @@ cva6_tlb #(
     .lu_asid_i            (asid_i),
     .asid_to_be_flushed_i (asid_to_be_flushed_i),
     .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i),
-    .lu_vaddr_i           (lu_vaddr_i),
+    .lu_vaddr_i           (icache_areq_i.fetch_vaddr),
+    .lu_gpaddr_o(),
     .lu_content_o         (itlb_content),
 
     .lu_is_page_o(itlb_is_page),
@@ -164,6 +164,7 @@ cva6_tlb #(
 
 cva6_tlb #(
     .CVA6Cfg    (CVA6Cfg),
+    .HYP_EXT(HYP_EXT),
     .TLB_ENTRIES(DATA_TLB_ENTRIES),
     .ASID_WIDTH (ASID_WIDTH),
     .ASID_LEN (ASID_LEN),
@@ -182,7 +183,8 @@ cva6_tlb #(
     .lu_asid_i            (asid_i),
     .asid_to_be_flushed_i (asid_to_be_flushed_i),
     .vaddr_to_be_flushed_i(vaddr_to_be_flushed_i),
-    .lu_vaddr_i           (lsu_vaddr_i),
+    .lu_vaddr_i           (lsu_vaddr_i[0]),
+    .lu_gpaddr_o(),
     .lu_content_o         (dtlb_content),
 
     .lu_is_page_o(dtlb_is_page),