Mmu unify task 1 - sv32 and sv39 #74
Annotations
3 warnings
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core/load_store_unit.sv#L199
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/load_store_unit.sv:199:- .misaligned_ex_i(misaligned_exception),
core/load_store_unit.sv:200:- .lsu_is_store_i (st_translation_req),
core/load_store_unit.sv:201:- .lsu_req_i (translation_req),
core/load_store_unit.sv:202:- .lsu_vaddr_i (mmu_lsu_vaddr_i),
core/load_store_unit.sv:203:- .lsu_valid_o (translation_valid),
core/load_store_unit.sv:204:- .lsu_paddr_o (mmu_paddr),
core/load_store_unit.sv:205:- .lsu_exception_o(mmu_exception),
core/load_store_unit.sv:206:- .lsu_dtlb_hit_o (dtlb_hit), // send in the same cycle as the request
core/load_store_unit.sv:207:- .lsu_dtlb_ppn_o (dtlb_ppn), // send in the same cycle as the request
core/load_store_unit.sv:199:+ .misaligned_ex_i (misaligned_exception),
core/load_store_unit.sv:200:+ .lsu_is_store_i (st_translation_req),
core/load_store_unit.sv:201:+ .lsu_req_i (translation_req),
core/load_store_unit.sv:202:+ .lsu_vaddr_i (mmu_lsu_vaddr_i),
core/load_store_unit.sv:203:+ .lsu_valid_o (translation_valid),
core/load_store_unit.sv:204:+ .lsu_paddr_o (mmu_paddr),
core/load_store_unit.sv:205:+ .lsu_exception_o (mmu_exception),
core/load_store_unit.sv:206:+ .lsu_dtlb_hit_o (dtlb_hit), // send in the same cycle as the request
core/load_store_unit.sv:207:+ .lsu_dtlb_ppn_o (dtlb_ppn), // send in the same cycle as the request
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core/load_store_unit.sv#L209
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/load_store_unit.sv:209:- .req_port_i (dcache_req_ports_i[0]),
core/load_store_unit.sv:210:- .req_port_o (dcache_req_ports_o[0]),
core/load_store_unit.sv:209:+ .req_port_i (dcache_req_ports_i[0]),
core/load_store_unit.sv:210:+ .req_port_o (dcache_req_ports_o[0]),
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core/mmu_unify/cva6_tlb.sv#L302
[verible-verilog-format] reported by reviewdog 🐶
Raw Output:
core/mmu_unify/cva6_tlb.sv:302:-end
core/mmu_unify/cva6_tlb.sv:303:-
core/mmu_unify/cva6_tlb.sv:304:-// Just for checking
core/mmu_unify/cva6_tlb.sv:305:-function int countSetBits(logic [TLB_ENTRIES-1:0] vector);
core/mmu_unify/cva6_tlb.sv:306:- automatic int count = 0;
core/mmu_unify/cva6_tlb.sv:307:- foreach (vector[idx]) begin
core/mmu_unify/cva6_tlb.sv:308:- count += vector[idx];
core/mmu_unify/cva6_tlb.sv:309:- end
core/mmu_unify/cva6_tlb.sv:310:- return count;
core/mmu_unify/cva6_tlb.sv:311:-endfunction
core/mmu_unify/cva6_tlb.sv:312:-
core/mmu_unify/cva6_tlb.sv:313:-assert property (@(posedge clk_i) (countSetBits(lu_hit) <= 1))
core/mmu_unify/cva6_tlb.sv:314:-else begin
core/mmu_unify/cva6_tlb.sv:315:- $error("More then one hit in TLB!");
core/mmu_unify/cva6_tlb.sv:316:- $stop();
core/mmu_unify/cva6_tlb.sv:317:-end
core/mmu_unify/cva6_tlb.sv:318:-assert property (@(posedge clk_i) (countSetBits(replace_en) <= 1))
core/mmu_unify/cva6_tlb.sv:319:-else begin
core/mmu_unify/cva6_tlb.sv:320:- $error("More then one TLB entry selected for next replace!");
core/mmu_unify/cva6_tlb.sv:321:- $stop();
core/mmu_unify/cva6_tlb.sv:322:-end
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