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Merge commit 'fe59754f31a4c818d3a0fd025c3e61ee41a7e9c4' into 40x_yaml…
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silabs-robin committed Sep 28, 2023
2 parents d5ef816 + fe59754 commit 0172a72
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1 change: 1 addition & 0 deletions env/uvme/uvma_cv32e40x_core_cntrl_agent.sv
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Expand Up @@ -163,6 +163,7 @@ function void uvma_cv32e40x_core_cntrl_agent_c::configure_iss();
$fwrite(fh, $sformatf("--override %s/mhartid=%0d\n", refpath, cfg.mhartid));
$fwrite(fh, $sformatf("--override %s/mimpid=%0d\n", refpath, cfg.mimpid));
$fwrite(fh, $sformatf("--override %s/startaddress=0x%08x\n", refpath, cfg.boot_addr));
$fwrite(fh, $sformatf("--override %s/reset_address=0x%08x\n", refpath, cfg.boot_addr));
// Specification forces mtvec[0] high at reset regardless of bootstrap pin state of mtvec_addr_i]0]
$fwrite(fh, $sformatf("--override %s/mtvec_mask=0xffffff8%1d\n", refpath, (cfg.clic_interrupt_enable ? 0 : 1)));
$fwrite(fh, $sformatf("--override %s/mtvec=0x%08x\n", refpath, cfg.mtvec_addr | (cfg.clic_interrupt_enable ? 32'b11 : 32'b1)));
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2 changes: 1 addition & 1 deletion sim/ExternalRepos.mk
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Expand Up @@ -15,7 +15,7 @@ export SHELL = /bin/bash

CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40x
CV_CORE_BRANCH ?= master
CV_CORE_HASH ?= 9b34c49e55ba816bfa18d6c7233667b17ddcf5c4
CV_CORE_HASH ?= b54d605ebd5b98bbd114d72115f9755a785cfeaa
CV_CORE_TAG ?= none

#RISCVDV_REPO ?= https://github.com/google/riscv-dv
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34 changes: 19 additions & 15 deletions sim/tools/xrun/README.md
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@@ -1,24 +1,28 @@
## Xcelium tools directory
## Xcelium Tools Directory

Various Xcelium-based utilities and scripts.
Xcelium-based utilities and scripts.

### Simulator control scripts

These TCL scripts can be passed to Xcelium by the core-v-verif Makefiles when using Xcelium. The following scripts are currently supported:
### Simulator Control Scripts

| Script | Usage |
|--------|-------|
| probe.tcl | Generates probes for waveform database viewable with Cadence SimVision. Invoked when WAVES=1 passed to the make test command |
| indago.tcl | Generates probes for waveform database viewable with Cadence Indago. Invokedf when WAVEs=1 ADV_DEBUG=1 passed to the make test command |
These scripts can be passed to Xcelium by the core-v-verif Makefiles.
The following scripts are currently supported:

### Coverage refinement files
| Script | Usage |
|------------|-------|
| probe.tcl | Generates probes for waveform database viewable with Cadence SimVision. Invoked when WAVES=1 passed to the make test command |
| indago.tcl | Generates probes for waveform database viewable with Cadence Indago. Invokedf when WAVES=1 ADV_DEBUG=1 passed to the make test command |

These XML files should be created using coverage tools such as IMC or Vmanager. These are used to generate coverage reports that focus on necessary coverage while removing exceptions that are unhittable or not significant for the design being verified.

### Coverage Refinement Files

These refinement files should be created using coverage tools such as IMC or Vmanager.
They are used to generate coverage reports that focus on necessary coverage, while removing exceptions that are unhittable or not significant for the design being verified.

*Note that some files are automatically generated and some are manually maintained. This is indicated in the table.*

| File | Maintenance | Description |
|------|-------------|-------------|
| cv32e40x.hierarchy.vRefine | Manual | Removes hierarchies from coverage database that are not to be considered for coverage (e.g. testbench |
| cv32e40x.auto.vRefine | Automatic | Auto-generated refinements based on parameter usage for the CV32E40X without PULP extensions. *Do not manually edit* |
| cv32e40x.manual.vRefine | Manual | Manually added coverage exception based on deesign verification reviews. |
| File | Maintenance | Description |
|-----------------------------------|-------------|-------------|
| cv32e40x.non_dut_code_cov.vRefine | Manual | Removes non-DUT code coverage from coverage database, that are not to be considered for coverage (e.g. testbench) |
| cv32e40x.auto.vRefine | Automatic | Auto-generated refinements based on parameter usage for the CV32E40X without PULP extensions. *Do not manually edit* |
| cv32e40x.manual.vRefine | Manual | Manually added coverage exception based on deesign verification reviews. |
30 changes: 0 additions & 30 deletions sim/tools/xrun/cv32e40x.hierarchy.vRefine

This file was deleted.

15 changes: 15 additions & 0 deletions sim/tools/xrun/cv32e40x.manual_expression_cov_todo.vRefine
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<refinement-file-root>
<information comment-version="1" creation-time="Fri 08 Sep 2023 16:33:54 CEST" creator="krdosvik" csCheck="true" save-ref-method="seq" tool-version="Cadence vManager21.03" rules-signature-c="a9ecb50162bf96bfaf018ddd1467b61">
<ucm-files>
<ucm-file domain="icc" modelCheckSum="869849222" path="icc_33d8d886_6e15cd1e.ucm(merged)"></ucm-file>
</ucm-files>
<ccf-files>
<ccf-file content="# ----------------------------------------------------------------------------------;# General coverage configuration options;# ----------------------------------------------------------------------------------;;# Setting Constant Object Marking and enabling log for it;set_com -log;;# Disable scoring of implicit else and default case blocks;set_implicit_block_scoring -off;;# Remove empty instances from coverage hierarchy;deselect_coverage -remove_empty_instances;;# Enable resilience from code changes;set_refinement_resilience;;# Improve expression coverage performance;set_optimize -vlog_prune_on;;# Set glitch strobes;set_glitch_strobe 1ps;;# Enable coverage for type parameterized modules;set_parameterized_module_coverage -type_parameters_only;;# Enable coverage for expressions containing inside operator;set_expr_scoring -inside;;# ----------------------------------------------------------------------------------;# FSM coverage configruation;# ----------------------------------------------------------------------------------;;# Enable scoring state hold arcs in FSM;set_fsm_scoring -hold_transition;;# ----------------------------------------------------------------------------------;# Expression coverage configuration;# ----------------------------------------------------------------------------------;;# Setting expression scoring for all operators (not only boolean (|| &amp;&amp;) and VHDL (AND OR NOR NAND);set_expr_coverable_operators -all;set_expr_coverable_statements -all;;# ----------------------------------------------------------------------------------;# Toggle coverage configuration;# ----------------------------------------------------------------------------------;;# Toggle coverage smart refinement (refinement for toggle with traverse hierarchy);set_toggle_smart_refinement;;# ----------------------------------------------------------------------------------;# Covergroup coverage configuration;# ----------------------------------------------------------------------------------;set_covergroup -new_instance_reporting;;# ----------------------------------------------------------------------------------;# Instances/modules to remove from coverage;# For performance and to avoid spurious warnings, remove these modules from code coverage collection;# ----------------------------------------------------------------------------------;deselect_coverage -all -instance uvmt_cv32e40x_tb.imperas_dv...;" path="/work/mcu40nm/ip_rad_riscv/mdx_cv32e40x_xrun_regress_full_no_ISS/clones/27/core-v-verif/cv32e40x/sim/tools/xrun/covfile.tcl"></ccf-file>
</ccf-files>
</information>
<rules>
</rules>
<cache-map>
</cache-map>
</refinement-file-root>
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