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[RISCV] Update format of xcvmem instructions #82

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[RISCV] Update format of xcvmem instructions #82

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32 changes: 16 additions & 16 deletions llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -494,36 +494,36 @@ let Predicates = [HasExtXcvbi], hasSideEffects = 0, mayLoad = 0, mayStore = 0, i
let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
// Register-Immediate load with post-increment
def CV_LB_ri_inc : RVInstLoad_ri_inc<0b000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
"cv.lb", "$rd, ${imm12}(${rs1}!)", []>,
"cv.lb", "$rd, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_LBU_ri_inc : RVInstLoad_ri_inc<0b100, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
"cv.lbu", "$rd, ${imm12}(${rs1}!)", []>,
"cv.lbu", "$rd, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_LH_ri_inc : RVInstLoad_ri_inc<0b001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
"cv.lh", "$rd, ${imm12}(${rs1}!)", []>,
"cv.lh", "$rd, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_LHU_ri_inc : RVInstLoad_ri_inc<0b101, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
"cv.lhu", "$rd, ${imm12}(${rs1}!)", []>,
"cv.lhu", "$rd, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_LW_ri_inc : RVInstLoad_ri_inc<0b010, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
"cv.lw", "$rd, ${imm12}(${rs1}!)", []>,
"cv.lw", "$rd, (${rs1}), ${imm12}", []>,
Sched<[]>;

// Register-Register load with post-increment
def CV_LB_rr_inc : RVInstLoad_rr_inc<0b0000000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
"cv.lb", "$rd, ${rs2}(${rs1}!)", []>,
"cv.lb", "$rd, (${rs1}), ${rs2}", []>,
Sched<[]>;
def CV_LBU_rr_inc : RVInstLoad_rr_inc<0b0001000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
"cv.lbu", "$rd, ${rs2}(${rs1}!)", []>,
"cv.lbu", "$rd, (${rs1}), ${rs2}", []>,
Sched<[]>;
def CV_LH_rr_inc : RVInstLoad_rr_inc<0b0000001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
"cv.lh", "$rd, ${rs2}(${rs1}!)", []>,
"cv.lh", "$rd, (${rs1}), ${rs2}", []>,
Sched<[]>;
def CV_LHU_rr_inc : RVInstLoad_rr_inc<0b0001001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
"cv.lhu", "$rd, ${rs2}(${rs1}!)", []>,
"cv.lhu", "$rd, (${rs1}), ${rs2}", []>,
Sched<[]>;
def CV_LW_rr_inc : RVInstLoad_rr_inc<0b0000010, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
"cv.lw", "$rd, ${rs2}(${rs1}!)", []>,
"cv.lw", "$rd, (${rs1}), ${rs2}", []>,
Sched<[]>;
} // Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1"

Expand All @@ -550,24 +550,24 @@ let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0 i
let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
// Register-Immediate store with post-increment
def CV_SB_ri_inc : RVInstStore_ri_inc<0b000, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
"cv.sb", "$rs2, ${imm12}(${rs1}!)", []>,
"cv.sb", "$rs2, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_SH_ri_inc : RVInstStore_ri_inc<0b001, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
"cv.sh", "$rs2, ${imm12}(${rs1}!)", []>,
"cv.sh", "$rs2, (${rs1}), ${imm12}", []>,
Sched<[]>;
def CV_SW_ri_inc : RVInstStore_ri_inc<0b010, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
"cv.sw", "$rs2, ${imm12}(${rs1}!)", []>,
"cv.sw", "$rs2, (${rs1}), ${imm12}", []>,
Sched<[]>;

// Register-Register store with post-increment
def CV_SB_rr_inc : RVInstStore_rr_inc<0b011, 0b0010000, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
"cv.sb", "$rs2, ${rs3}(${rs1}!)", []>,
"cv.sb", "$rs2, (${rs1}), ${rs3}", []>,
Sched<[]>;
def CV_SH_rr_inc : RVInstStore_rr_inc<0b011, 0b0010001, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
"cv.sh", "$rs2, ${rs3}(${rs1}!)", []>,
"cv.sh", "$rs2, (${rs1}), ${rs3}", []>,
Sched<[]>;
def CV_SW_rr_inc : RVInstStore_rr_inc<0b011, 0b0010010, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
"cv.sw", "$rs2, ${rs3}(${rs1}!)", []>,
"cv.sw", "$rs2, (${rs1}), ${rs3}", []>,
Sched<[]>;
} // Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1"

Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/RISCV/corev/mem.ll
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+xcvmem -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+xcvmem -verify-machineinstrs < %s \
; RUN: | FileCheck %s

define <2 x i32> @lb_ri_inc(i8* %a) {
; CHECK-LABEL: lb_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lb a1, 42(a0!)
; CHECK-NEXT: cv.lb a1, (a0), 42
; CHECK-NEXT: ret
%1 = load i8, i8* %a
%2 = sext i8 %1 to i32
Expand All @@ -19,7 +19,7 @@ define <2 x i32> @lb_ri_inc(i8* %a) {
define <2 x i32> @lb_rr_inc(i8* %a, i32 %b) {
; CHECK-LABEL: lb_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lb a1, a1(a0!)
; CHECK-NEXT: cv.lb a1, (a0), a1
; CHECK-NEXT: ret
%1 = load i8, i8* %a
%2 = sext i8 %1 to i32
Expand All @@ -44,7 +44,7 @@ define i32 @lb_rr(i8* %a, i32 %b) {
define <2 x i32> @lbu_ri_inc(i8* %a) {
; CHECK-LABEL: lbu_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lbu a1, 42(a0!)
; CHECK-NEXT: cv.lbu a1, (a0), 42
; CHECK-NEXT: ret
%1 = load i8, i8* %a
%2 = zext i8 %1 to i32
Expand All @@ -58,7 +58,7 @@ define <2 x i32> @lbu_ri_inc(i8* %a) {
define <2 x i32> @lbu_rr_inc(i8* %a, i32 %b) {
; CHECK-LABEL: lbu_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lbu a1, a1(a0!)
; CHECK-NEXT: cv.lbu a1, (a0), a1
; CHECK-NEXT: ret
%1 = load i8, i8* %a
%2 = zext i8 %1 to i32
Expand All @@ -83,7 +83,7 @@ define i32 @lbu_rr(i8* %a, i32 %b) {
define <2 x i32> @lh_ri_inc(i16* %a) {
; CHECK-LABEL: lh_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lh a1, 84(a0!)
; CHECK-NEXT: cv.lh a1, (a0), 84
; CHECK-NEXT: ret
%1 = load i16, i16* %a
%2 = sext i16 %1 to i32
Expand All @@ -98,7 +98,7 @@ define <2 x i32> @lh_rr_inc(i16* %a, i32 %b) {
; CHECK-LABEL: lh_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: cv.lh a1, a1(a0!)
; CHECK-NEXT: cv.lh a1, (a0), a1
; CHECK-NEXT: ret
%1 = load i16, i16* %a
%2 = sext i16 %1 to i32
Expand All @@ -124,7 +124,7 @@ define i32 @lh_rr(i16* %a, i32 %b) {
define <2 x i32> @lhu_ri_inc(i16* %a) {
; CHECK-LABEL: lhu_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lhu a1, 84(a0!)
; CHECK-NEXT: cv.lhu a1, (a0), 84
; CHECK-NEXT: ret
%1 = load i16, i16* %a
%2 = zext i16 %1 to i32
Expand All @@ -139,7 +139,7 @@ define <2 x i32> @lhu_rr_inc(i16* %a, i32 %b) {
; CHECK-LABEL: lhu_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: cv.lhu a1, a1(a0!)
; CHECK-NEXT: cv.lhu a1, (a0), a1
; CHECK-NEXT: ret
%1 = load i16, i16* %a
%2 = zext i16 %1 to i32
Expand All @@ -165,7 +165,7 @@ define i32 @lhu_rr(i16* %a, i32 %b) {
define <2 x i32> @lw_ri_inc(i32* %a) {
; CHECK-LABEL: lw_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.lw a1, 168(a0!)
; CHECK-NEXT: cv.lw a1, (a0), 168
; CHECK-NEXT: ret
%1 = load i32, i32* %a
%2 = getelementptr i32, i32* %a, i32 42
Expand All @@ -179,7 +179,7 @@ define <2 x i32> @lw_rr_inc(i32* %a, i32 %b) {
; CHECK-LABEL: lw_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: cv.lw a1, a1(a0!)
; CHECK-NEXT: cv.lw a1, (a0), a1
; CHECK-NEXT: ret
%1 = load i32, i32* %a
%2 = getelementptr i32, i32* %a, i32 %b
Expand All @@ -203,7 +203,7 @@ define i32 @lw_rr(i32* %a, i32 %b) {
define i8* @sb_ri_inc(i8* %a, i8 %b) {
; CHECK-LABEL: sb_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.sb a1, 42(a0!)
; CHECK-NEXT: cv.sb a1, (a0), 42
; CHECK-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 42
Expand All @@ -213,7 +213,7 @@ define i8* @sb_ri_inc(i8* %a, i8 %b) {
define i8* @sb_rr_inc(i8* %a, i8 %b, i32 %c) {
; CHECK-LABEL: sb_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.sb a1, a2(a0!)
; CHECK-NEXT: cv.sb a1, (a0), a2
; CHECK-NEXT: ret
store i8 %b, i8* %a
%1 = getelementptr i8, i8* %a, i32 %c
Expand All @@ -233,7 +233,7 @@ define void @sb_rr(i8* %a, i8 %b, i32 %c) {
define i16* @sh_ri_inc(i16* %a, i16 %b) {
; CHECK-LABEL: sh_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.sh a1, 84(a0!)
; CHECK-NEXT: cv.sh a1, (a0), 84
; CHECK-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 42
Expand All @@ -244,7 +244,7 @@ define i16* @sh_rr_inc(i16* %a, i16 %b, i32 %c) {
; CHECK-LABEL: sh_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a2, a2, 1
; CHECK-NEXT: cv.sh a1, a2(a0!)
; CHECK-NEXT: cv.sh a1, (a0), a2
; CHECK-NEXT: ret
store i16 %b, i16* %a
%1 = getelementptr i16, i16* %a, i32 %c
Expand All @@ -265,7 +265,7 @@ define void @sh_rr(i16* %a, i16 %b, i32 %c) {
define i32* @sw_ri_inc(i32* %a, i32 %b) {
; CHECK-LABEL: sw_ri_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: cv.sw a1, 168(a0!)
; CHECK-NEXT: cv.sw a1, (a0), 168
; CHECK-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 42
Expand All @@ -276,7 +276,7 @@ define i32* @sw_rr_inc(i32* %a, i32 %b, i32 %c) {
; CHECK-LABEL: sw_rr_inc:
; CHECK: # %bb.0:
; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: cv.sw a1, a2(a0!)
; CHECK-NEXT: cv.sw a1, (a0), a2
; CHECK-NEXT: ret
store i32 %b, i32* %a
%1 = getelementptr i32, i32* %a, i32 %c
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/MC/RISCV/corev/mem/lb-invalid.s
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Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR

cv.lb t0, 0(0!)
# CHECK-ERROR: expected register
cv.lb t0, (0), 0
# CHECK-ERROR: invalid operand for instruction

cv.lb 0, 0(t1!)
cv.lb 0, (t1), 0
# CHECK-ERROR: invalid operand for instruction

cv.lb t0, 0(t1)
# CHECK-ERROR: invalid operand for instruction

cv.lb t0, 2048(t1!)
cv.lb t0, (t1), 2048
# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]

cv.lb t0, t1(0!)
# CHECK-ERROR: expected register
cv.lb t0, (0), t1
# CHECK-ERROR: invalid operand for instruction

cv.lb 0, t1(t1!)
cv.lb 0, (t1), t1
# CHECK-ERROR: invalid operand for instruction

cv.lb t0, t1(0)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/MC/RISCV/corev/mem/lb.s
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Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR

cv.lb t0, 0(t1!)
# CHECK-INSTR: cv.lb t0, 0(t1!)
cv.lb t0, (t1), 0
# CHECK-INSTR: cv.lb t0, (t1), 0
# CHECK-ENCODING: [0x8b,0x02,0x03,0x00]

cv.lb a0, 2047(a1!)
# CHECK-INSTR: cv.lb a0, 2047(a1!)
cv.lb a0, (a1), 2047
# CHECK-INSTR: cv.lb a0, (a1), 2047
# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f]



cv.lb t0, t2(t1!)
# CHECK-INSTR: cv.lb t0, t2(t1!)
cv.lb t0, (t1), t2
# CHECK-INSTR: cv.lb t0, (t1), t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x00]

cv.lb a0, a2(a1!)
# CHECK-INSTR: cv.lb a0, a2(a1!)
cv.lb a0, (a1), a2
# CHECK-INSTR: cv.lb a0, (a1), a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00]


Expand Down
14 changes: 7 additions & 7 deletions llvm/test/MC/RISCV/corev/mem/lbu-invalid.s
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Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR

cv.lbu t0, 0(0!)
# CHECK-ERROR: expected register
cv.lbu t0, (0), 0
# CHECK-ERROR: invalid operand for instruction

cv.lbu 0, 0(t1!)
cv.lbu 0, (t1), 0
# CHECK-ERROR: invalid operand for instruction

cv.lbu t0, 0(t1)
# CHECK-ERROR: invalid operand for instruction

cv.lbu t0, 2048(t1!)
cv.lbu t0, (t1), 2048
# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]

cv.lbu t0, t1(0!)
# CHECK-ERROR: expected register
cv.lbu t0, (0), t1
# CHECK-ERROR: invalid operand for instruction

cv.lbu 0, t1(t1!)
cv.lbu 0, (t1), t1
# CHECK-ERROR: invalid operand for instruction

cv.lbu t0, t1(0)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/MC/RISCV/corev/mem/lbu.s
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Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR

cv.lbu t0, 0(t1!)
# CHECK-INSTR: cv.lbu t0, 0(t1!)
cv.lbu t0, (t1), 0
# CHECK-INSTR: cv.lbu t0, (t1), 0
# CHECK-ENCODING: [0x8b,0x42,0x03,0x00]

cv.lbu a0, 2047(a1!)
# CHECK-INSTR: cv.lbu a0, 2047(a1!)
cv.lbu a0, (a1), 2047
# CHECK-INSTR: cv.lbu a0, (a1), 2047
# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f]



cv.lbu t0, t2(t1!)
# CHECK-INSTR: cv.lbu t0, t2(t1!)
cv.lbu t0, (t1), t2
# CHECK-INSTR: cv.lbu t0, (t1), t2
# CHECK-ENCODING: [0xab,0x32,0x73,0x10]

cv.lbu a0, a2(a1!)
# CHECK-INSTR: cv.lbu a0, a2(a1!)
cv.lbu a0, (a1), a2
# CHECK-INSTR: cv.lbu a0, (a1), a2
# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10]


Expand Down
14 changes: 7 additions & 7 deletions llvm/test/MC/RISCV/corev/mem/lh-invalid.s
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Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR

cv.lh t0, 0(0!)
# CHECK-ERROR: expected register
cv.lh t0, (0), 0
# CHECK-ERROR: invalid operand for instruction

cv.lh 0, 0(t1!)
cv.lh 0, (t1), 0
# CHECK-ERROR: invalid operand for instruction

cv.lh t0, 0(t1)
# CHECK-ERROR: invalid operand for instruction

cv.lh t0, 2048(t1!)
cv.lh t0, (t1), 2048
# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]

cv.lh t0, t1(0!)
# CHECK-ERROR: expected register
cv.lh t0, (0), t1
# CHECK-ERROR: invalid operand for instruction

cv.lh 0, t1(t1!)
cv.lh 0, (t1), t1
# CHECK-ERROR: invalid operand for instruction

cv.lh t0, t1(0)
Expand Down
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