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[RISCV][Clang] Implement Xcvmac clang builtins
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Implement Xcvmac clang builtins. Capitalize "N" and "RN" suffix of instrinsics.

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst
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@realqhc @PaoloS02
realqhc authored and PaoloS02 committed Oct 11, 2023
1 parent aea0c3a commit fbe6071
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19 changes: 19 additions & 0 deletions clang/include/clang/Basic/BuiltinsRISCVCOREV.def
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Original file line number Diff line number Diff line change
Expand Up @@ -177,6 +177,25 @@ TARGET_BUILTIN(bitmanip_cnt, "UZiUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_ror, "UZiUZiUZi", "nc", "xcvbitmanip")
TARGET_BUILTIN(bitmanip_bitrev, "UZiUZiIUcIUc", "nc", "xcvbitmanip")

TARGET_BUILTIN(mac_mac, "UZiUZiUZiUZi", "nc", "xcvmac")
TARGET_BUILTIN(mac_msu, "UZiUZiUZiUZi", "nc", "xcvmac")
TARGET_BUILTIN(mac_muluN, "UZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulhhuN, "UZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulsN, "SZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulhhsN, "SZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_muluRN, "UZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulhhuRN, "UZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulsRN, "SZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_mulhhsRN, "SZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_macuN, "UZiUZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_machhuN, "UZiUZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_macsN, "SZiUZiUZiSZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_machhsN, "SZiUZiUZiSZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_macuRN, "UZiUZiUZiSZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_machhuRN, "UZiUZiUZiUZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_macsRN, "SZiUZiUZiSZiUc", "nc", "xcvmac")
TARGET_BUILTIN(mac_machhsRN, "SZiUZiUZiSZiUc", "nc", "xcvmac")

#undef BUILTIN
#undef TARGET_BUILTIN
#undef PSEUDO_BUILTIN
309 changes: 309 additions & 0 deletions clang/test/CodeGen/RISCV/corev-intrinsics/mac.c
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@@ -0,0 +1,309 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvmac -emit-llvm %s -o - \
// RUN: | FileCheck %s


#include <stdint.h>



// CHECK-LABEL: @test_mac_mac(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.mac(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_mac(int32_t x, int32_t y, int32_t z) {
return __builtin_riscv_cv_mac_mac(x, y, z);
}

// CHECK-LABEL: @test_mac_msu(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.msu(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_msu(int32_t x, int32_t y, int32_t z) {
return __builtin_riscv_cv_mac_msu(x, y, z);
}

// CHECK-LABEL: @test_mac_muluN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.muluN(i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK-NEXT: ret i32 [[TMP2]]
//
uint32_t test_mac_muluN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_muluN(x, y, 0);
}

// CHECK-LABEL: @test_mac_mulhhuN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhuN(i32 [[TMP0]], i32 [[TMP1]], i32 0)
// CHECK-NEXT: ret i32 [[TMP2]]
//
uint32_t test_mac_mulhhuN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulhhuN(x, y, 0);
}

// CHECK-LABEL: @test_mac_mulsN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulsN(i32 [[TMP0]], i32 [[TMP1]], i32 1)
// CHECK-NEXT: ret i32 [[TMP2]]
//
int32_t test_mac_mulsN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulsN(x, y, 1);
}

// CHECK-LABEL: @test_mac_mulhhsN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhsN(i32 [[TMP0]], i32 [[TMP1]], i32 1)
// CHECK-NEXT: ret i32 [[TMP2]]
//
int32_t test_mac_mulhhsN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulhhsN(x, y, 1);
}

// CHECK-LABEL: @test_mac_muluRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.muluRN(i32 [[TMP0]], i32 [[TMP1]], i32 2)
// CHECK-NEXT: ret i32 [[TMP2]]
//
uint32_t test_mac_muluRN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_muluRN(x, y, 2);
}

// CHECK-LABEL: @test_mac_mulhhuRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhuRN(i32 [[TMP0]], i32 [[TMP1]], i32 2)
// CHECK-NEXT: ret i32 [[TMP2]]
//
uint32_t test_mac_mulhhuRN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulhhuRN(x, y, 2);
}

// CHECK-LABEL: @test_mac_mulsRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulsRN(i32 [[TMP0]], i32 [[TMP1]], i32 3)
// CHECK-NEXT: ret i32 [[TMP2]]
//
int32_t test_mac_mulsRN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulsRN(x, y, 3);
}

// CHECK-LABEL: @test_mac_mulhhsRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.mac.mulhhsRN(i32 [[TMP0]], i32 [[TMP1]], i32 3)
// CHECK-NEXT: ret i32 [[TMP2]]
//
int32_t test_mac_mulhhsRN(uint32_t x, uint32_t y) {
return __builtin_riscv_cv_mac_mulhhsRN(x, y, 3);
}

// 16-bit x 16-bit multiply-accumulate
// CHECK-LABEL: @test_mac_macuN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macuN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 4)
// CHECK-NEXT: ret i32 [[TMP3]]
//
uint32_t test_mac_macuN(uint32_t x, uint32_t y, uint32_t z) {
return __builtin_riscv_cv_mac_macuN(x, y, z, 4);
}

// CHECK-LABEL: @test_mac_machhuN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhuN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 4)
// CHECK-NEXT: ret i32 [[TMP3]]
//
uint32_t test_mac_machhuN(uint32_t x, uint32_t y, uint32_t z) {
return __builtin_riscv_cv_mac_machhuN(x, y, z, 4);
}

// CHECK-LABEL: @test_mac_macsN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macsN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 5)
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_macsN(uint32_t x, uint32_t y, int32_t z) {
return __builtin_riscv_cv_mac_macsN(x, y, z, 5);
}

// CHECK-LABEL: @test_mac_machhsN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhsN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 5)
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_machhsN(uint32_t x, uint32_t y, int32_t z) {
return __builtin_riscv_cv_mac_machhsN(x, y, z, 5);
}

// CHECK-LABEL: @test_mac_macuRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macuRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 6)
// CHECK-NEXT: ret i32 [[TMP3]]
//
uint32_t test_mac_macuRN(uint32_t x, uint32_t y, uint32_t z) {
return __builtin_riscv_cv_mac_macuRN(x, y, z, 6);
}

// CHECK-LABEL: @test_mac_machhuRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhuRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 6)
// CHECK-NEXT: ret i32 [[TMP3]]
//
uint32_t test_mac_machhuRN(uint32_t x, uint32_t y, uint32_t z) {
return __builtin_riscv_cv_mac_machhuRN(x, y, z, 6);
}

// CHECK-LABEL: @test_mac_macsRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.macsRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 7)
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_macsRN(uint32_t x, uint32_t y, int32_t z) {
return __builtin_riscv_cv_mac_macsRN(x, y, z, 7);
}

// CHECK-LABEL: @test_mac_machhsRN(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Y_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[Z_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4
// CHECK-NEXT: store i32 [[Y:%.*]], ptr [[Y_ADDR]], align 4
// CHECK-NEXT: store i32 [[Z:%.*]], ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[Y_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Z_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.riscv.cv.mac.machhsRN(i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]], i32 7)
// CHECK-NEXT: ret i32 [[TMP3]]
//
int32_t test_mac_machhsRN(uint32_t x, uint32_t y, int32_t z) {
return __builtin_riscv_cv_mac_machhsRN(x, y, z, 7);
}
34 changes: 17 additions & 17 deletions llvm/include/llvm/IR/IntrinsicsRISCV.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1751,23 +1751,23 @@ class ScalarCoreVMacGprGprGprImmIntrinsic
def int_riscv_cv_mac_mac : ScalarCoreVMacGprGprGprIntrinsic;
def int_riscv_cv_mac_msu : ScalarCoreVMacGprGprGprIntrinsic;

def int_riscv_cv_mac_mulun : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhun : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulsn : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhsn : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulurn : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhurn : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulsrn : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhsrn : ScalarCoreVMacGprGPRImmIntrinsic;

def int_riscv_cv_mac_macun : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhun : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macsn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhsn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macurn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhurn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macsrn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhsrn : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_muluN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhuN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulsN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhsN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_muluRN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhuRN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulsRN : ScalarCoreVMacGprGPRImmIntrinsic;
def int_riscv_cv_mac_mulhhsRN : ScalarCoreVMacGprGPRImmIntrinsic;

def int_riscv_cv_mac_macuN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhuN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macsN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhsN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_macsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;

def int_riscv_cv_elw_elw
: Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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