[RISCV] Update naming of cv.slet

openhwgroup · Sep 19, 2023 · 8cb5834 · 8cb5834
1 parent f5d1f87
commit 8cb5834
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Showing 7 changed files with 72 additions and 22 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
@@ -386,11 +386,11 @@ let Predicates = [HasExtXcvalu], hasSideEffects = 0, mayLoad = 0, mayStore = 0 i
   def CV_ABS    : RVInstAlu_r<0b0101000, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
                               "cv.abs", "$rd, $rs1", []>,
                   Sched<[]>;
-  def CV_SLET   : RVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
-                               "cv.slet", "$rd, $rs1, $rs2", []>,
+  def CV_SLE   : RVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.sle", "$rd, $rs1, $rs2", []>,
                   Sched<[]>;
-  def CV_SLETU  : RVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
-                               "cv.sletu", "$rd, $rs1, $rs2", []>,
+  def CV_SLEU  : RVInstAlu_rr<0b0101010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.sleu", "$rd, $rs1, $rs2", []>,
                   Sched<[]>;
   def CV_MIN    : RVInstAlu_rr<0b0101011, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
                                "cv.min", "$rd, $rs1, $rs2", []>,
@@ -484,6 +484,12 @@ let Predicates = [HasExtXcvalu], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
 
 } // Predicates = [HasExtXcvalu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM1.Value, Constraints = "$rd = $rd_wb"
 
+let Predicates = [HasExtXcvalu] in {
+  // Xcvalu Pseudo Instructions
+  def : InstAlias<"cv.slet $rd, $rs1, $rs2", (CV_SLE GPR:$rd, GPR:$rs1, GPR:$rs2), 0>;
+  def : InstAlias<"cv.sletu $rd, $rs1, $rs2", (CV_SLEU GPR:$rd, GPR:$rs1, GPR:$rs2), 0>;
+} // Predicates = [HasExtXcvalu]
+
 let Predicates = [HasExtXcvbi], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isBranch = 1, isTerminator = 1 in {
   // Immediate branching operations
   def CV_BEQIMM : RVInstImmBranch<0b110, (outs), (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
@@ -825,8 +831,8 @@ multiclass PatCoreVAluGprGprImm <Intrinsic intr> {
 let Predicates = [HasExtXcvalu] in {
 
   def : Pat<(abs GPR:$rs1), (CV_ABS GPR:$rs1)>;
-  def : PatGprGpr<setle, CV_SLET>;
-  def : PatGprGpr<setule, CV_SLETU>;
+  def : PatGprGpr<setle, CV_SLE>;
+  def : PatGprGpr<setule, CV_SLEU>;
   def : PatGprGpr<smin, CV_MIN>;
   def : PatGprGpr<umin, CV_MINU>;
   def : PatGprGpr<smax, CV_MAX>;
@@ -883,8 +889,8 @@ let Predicates = [HasExtXcvalu] in {
             (CV_SUBURNR GPR:$rd, GPR:$rs1, GPR:$rs2)>;
 
   def : PatCoreVAluGpr<"abs", "ABS">;
-  def : PatCoreVAluGprGpr<"slet", "SLET">;
-  def : PatCoreVAluGprGpr<"sletu", "SLETU">;
+  def : PatCoreVAluGprGpr<"slet", "SLE">;
+  def : PatCoreVAluGprGpr<"sletu", "SLEU">;
   def : PatCoreVAluGprGpr<"min", "MIN">;
   def : PatCoreVAluGprGpr<"minu", "MINU">;
   def : PatCoreVAluGprGpr<"max", "MAX">;

diff --git a/llvm/test/CodeGen/RISCV/corev/alu.ll b/llvm/test/CodeGen/RISCV/corev/alu.ll
@@ -17,19 +17,19 @@ define i32 @abs(i32 %a) {
   ret i32 %1
 }
 
-define i1 @slet(i32 %a, i32 %b) {
-; CHECK-LABEL: slet:
+define i1 @sle(i32 %a, i32 %b) {
+; CHECK-LABEL: sle:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cv.slet a0, a0, a1
+; CHECK-NEXT:    cv.sle a0, a0, a1
 ; CHECK-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   ret i1 %1
 }
 
-define i1 @sletu(i32 %a, i32 %b) {
-; CHECK-LABEL: sletu:
+define i1 @sleu(i32 %a, i32 %b) {
+; CHECK-LABEL: sleu:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cv.sletu a0, a0, a1
+; CHECK-NEXT:    cv.sleu a0, a0, a1
 ; CHECK-NEXT:    ret
   %1 = icmp ule i32 %a, %b
   ret i1 %1
@@ -344,7 +344,7 @@ declare i32 @llvm.riscv.cv.alu.slet(i32, i32)
 define i32 @test.cv.alu.slet(i32 %a, i32 %b) {
 ; CHECK-LABEL: test.cv.alu.slet:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cv.slet a0, a0, a1
+; CHECK-NEXT:    cv.sle a0, a0, a1
 ; CHECK-NEXT:    ret
   %1 = call i32 @llvm.riscv.cv.alu.slet(i32 %a, i32 %b)
   ret i32 %1
@@ -355,7 +355,7 @@ declare i32 @llvm.riscv.cv.alu.sletu(i32, i32)
 define i32 @test.cv.alu.sletu(i32 %a, i32 %b) {
 ; CHECK-LABEL: test.cv.alu.sletu:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cv.sletu a0, a0, a1
+; CHECK-NEXT:    cv.sleu a0, a0, a1
 ; CHECK-NEXT:    ret
   %1 = call i32 @llvm.riscv.cv.alu.sletu(i32 %a, i32 %b)
   ret i32 %1

diff --git a/llvm/test/MC/RISCV/corev/alu/invalid.s b/llvm/test/MC/RISCV/corev/alu/invalid.s
@@ -6,6 +6,12 @@
 cv.abs t0, t1
 # CHECK-ERROR: instruction requires the following: 'Xcvalu' (ALU Operations)
 
+cv.sle t0, t1, t2
+# CHECK-ERROR: instruction requires the following: 'Xcvalu' (ALU Operations)
+
+cv.sleu t0, t1, t2
+# CHECK-ERROR: instruction requires the following: 'Xcvalu' (ALU Operations)
+
 cv.slet t0, t1, t2
 # CHECK-ERROR: instruction requires the following: 'Xcvalu' (ALU Operations)
 

diff --git a/llvm/test/MC/RISCV/corev/alu/slet-invalid.s b/llvm/test/MC/RISCV/corev/alu/slet-invalid.s
@@ -1,6 +1,21 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvalu %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
+cv.sle t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sle t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sle 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sle t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.sle t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
 cv.slet t0, t1, 0
 # CHECK-ERROR: invalid operand for instruction
 

diff --git a/llvm/test/MC/RISCV/corev/alu/slet.s b/llvm/test/MC/RISCV/corev/alu/slet.s
@@ -1,10 +1,18 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvalu -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
+cv.sle t0, t1, t2
+# CHECK-INSTR: cv.sle t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x52]
+
+cv.sle a0, a1, a2
+# CHECK-INSTR: cv.sle a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
+
 cv.slet t0, t1, t2
-# CHECK-INSTR: cv.slet t0, t1, t2
+# CHECK-INSTR: cv.sle t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x52]
 
 cv.slet a0, a1, a2
-# CHECK-INSTR: cv.slet a0, a1, a2
+# CHECK-INSTR: cv.sle a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
diff --git a/llvm/test/MC/RISCV/corev/alu/sletu-invalid.s b/llvm/test/MC/RISCV/corev/alu/sletu-invalid.s
@@ -1,6 +1,21 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvalu %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
+cv.sleu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sleu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sleu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sleu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.sleu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
 cv.sletu t0, t1, 0
 # CHECK-ERROR: invalid operand for instruction
 

diff --git a/llvm/test/MC/RISCV/corev/alu/sletu.s b/llvm/test/MC/RISCV/corev/alu/sletu.s
@@ -1,10 +1,10 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvalu -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
-cv.sletu t0, t1, t2
-# CHECK-INSTR: cv.sletu t0, t1, t2
+cv.sleu t0, t1, t2
+# CHECK-INSTR: cv.sleu t0, t1, t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x54]
 
-cv.sletu a0, a1, a2
-# CHECK-INSTR: cv.sletu a0, a1, a2
+cv.sleu a0, a1, a2
+# CHECK-INSTR: cv.sleu a0, a1, a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]