Update naming for xcvmem instructions

fix issue71 #71
openhwgroup · Aug 7, 2023 · 86301bf · 86301bf
1 parent 31e7028
commit 86301bf
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diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
@@ -494,36 +494,36 @@ let Predicates = [HasExtXcvbi], hasSideEffects = 0, mayLoad = 0, mayStore = 0, i
 let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1" in {
   // Register-Immediate load with post-increment
   def CV_LB_ri_inc  : RVInstLoad_ri_inc<0b000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
-                                        "cv.lb", "$rd, ${imm12}(${rs1}!)", []>,
+                                        "cv.lb", "$rd, (${rs1}), ${imm12}", []>,
                       Sched<[]>;
   def CV_LBU_ri_inc : RVInstLoad_ri_inc<0b100, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
-                                        "cv.lbu", "$rd, ${imm12}(${rs1}!)", []>,
+                                        "cv.lbu", "$rd, (${rs1}), ${imm12}", []>,
                       Sched<[]>;
   def CV_LH_ri_inc  : RVInstLoad_ri_inc<0b001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
-                                        "cv.lh", "$rd, ${imm12}(${rs1}!)", []>,
+                                        "cv.lh", "$rd, (${rs1}), ${imm12}", []>,
                       Sched<[]>;
   def CV_LHU_ri_inc : RVInstLoad_ri_inc<0b101, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
-                                        "cv.lhu", "$rd, ${imm12}(${rs1}!)", []>,
+                                        "cv.lhu", "$rd, (${rs1}), ${imm12}", []>,
                       Sched<[]>;
   def CV_LW_ri_inc  : RVInstLoad_ri_inc<0b010, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, simm12:$imm12),
-                                        "cv.lw", "$rd, ${imm12}(${rs1}!)", []>,
+                                        "cv.lw", "$rd, (${rs1}), ${imm12}", []>,
                       Sched<[]>;
 
   // Register-Register load with post-increment
   def CV_LB_rr_inc  : RVInstLoad_rr_inc<0b0000000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
-                                        "cv.lb", "$rd, ${rs2}(${rs1}!)", []>,
+                                        "cv.lb", "$rd, (${rs1}), ${rs2}", []>,
                       Sched<[]>;
   def CV_LBU_rr_inc : RVInstLoad_rr_inc<0b0001000, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
-                                        "cv.lbu", "$rd, ${rs2}(${rs1}!)", []>,
+                                        "cv.lbu", "$rd, (${rs1}), ${rs2}", []>,
                       Sched<[]>;
   def CV_LH_rr_inc  : RVInstLoad_rr_inc<0b0000001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
-                                        "cv.lh", "$rd, ${rs2}(${rs1}!)", []>,
+                                        "cv.lh", "$rd, (${rs1}), ${rs2}", []>,
                       Sched<[]>;
   def CV_LHU_rr_inc : RVInstLoad_rr_inc<0b0001001, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
-                                        "cv.lhu", "$rd, ${rs2}(${rs1}!)", []>,
+                                        "cv.lhu", "$rd, (${rs1}), ${rs2}", []>,
                       Sched<[]>;
   def CV_LW_rr_inc  : RVInstLoad_rr_inc<0b0000010, (outs GPR:$rd, GPR:$rs1_wb), (ins GPR:$rs1, GPR:$rs2),
-                                        "cv.lw", "$rd, ${rs2}(${rs1}!)", []>,
+                                        "cv.lw", "$rd, (${rs1}), ${rs2}", []>,
                       Sched<[]>;
 } // Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0, Constraints = "$rs1_wb = $rs1"
 
@@ -550,24 +550,24 @@ let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 1, mayStore = 0 i
 let Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1" in {
   // Register-Immediate store with post-increment
   def CV_SB_ri_inc : RVInstStore_ri_inc<0b000, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
-                                        "cv.sb", "$rs2, ${imm12}(${rs1}!)", []>,
+                                        "cv.sb", "$rs2, (${rs1}), ${imm12}", []>,
                      Sched<[]>;
   def CV_SH_ri_inc : RVInstStore_ri_inc<0b001, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
-                                        "cv.sh", "$rs2, ${imm12}(${rs1}!)", []>,
+                                        "cv.sh", "$rs2, (${rs1}), ${imm12}", []>,
                      Sched<[]>;
   def CV_SW_ri_inc : RVInstStore_ri_inc<0b010, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
-                                        "cv.sw", "$rs2, ${imm12}(${rs1}!)", []>,
+                                        "cv.sw", "$rs2, (${rs1}), ${imm12}", []>,
                      Sched<[]>;
 
   // Register-Register store with post-increment
   def CV_SB_rr_inc : RVInstStore_rr_inc<0b011, 0b0010000, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
-                                        "cv.sb", "$rs2, ${rs3}(${rs1}!)", []>,
+                                        "cv.sb", "$rs2, (${rs1}), ${rs3}", []>,
                      Sched<[]>;
   def CV_SH_rr_inc : RVInstStore_rr_inc<0b011, 0b0010001, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
-                                        "cv.sh", "$rs2, ${rs3}(${rs1}!)", []>,
+                                        "cv.sh", "$rs2, (${rs1}), ${rs3}", []>,
                      Sched<[]>;
   def CV_SW_rr_inc : RVInstStore_rr_inc<0b011, 0b0010010, (outs GPR:$rs1_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rs3),
-                                        "cv.sw", "$rs2, ${rs3}(${rs1}!)", []>,
+                                        "cv.sw", "$rs2, (${rs1}), ${rs3}", []>,
                      Sched<[]>;
 } // Predicates = [HasExtXcvmem], hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rs1_wb = $rs1"
 

diff --git a/llvm/test/MC/RISCV/corev/mem/lb-invalid.s b/llvm/test/MC/RISCV/corev/mem/lb-invalid.s
@@ -1,29 +1,32 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
-cv.lb t0, 0(0!)
-# CHECK-ERROR: expected register
+cv.lb t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
 
-cv.lb 0, 0(t1!)
+cv.lb 0, (t1), 0
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lb t0, 0(t1)
+cv.lb 0, (0), t2
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lb t0, 2048(t1!)
+cv.lb t0, (t1), -2049
 # CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lb t0, t1(0!)
-# CHECK-ERROR: expected register
+cv.lb t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lb 0, t1(t1!)
+cv.lb t0, (0), t1
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lb t0, t1(0)
-# CHECK-ERROR: expected register
-
-cv.lb 0, 0(t1)
+cv.lb 0, (t1), t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lb t0
 # CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lb t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/mem/lb.s b/llvm/test/MC/RISCV/corev/mem/lb.s
@@ -1,22 +1,22 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
-cv.lb t0, 0(t1!)
-# CHECK-INSTR: cv.lb t0, 0(t1!)
+cv.lb t0, (t1), 0
+# CHECK-INSTR: cv.lb t0, (t1), 0
 # CHECK-ENCODING: [0x8b,0x02,0x03,0x00]
 
-cv.lb a0, 2047(a1!)
-# CHECK-INSTR: cv.lb a0, 2047(a1!)
+cv.lb a0, (a1), 2047
+# CHECK-INSTR: cv.lb a0, (a1), 2047
 # CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f]
 
 
 
-cv.lb t0, t2(t1!)
-# CHECK-INSTR: cv.lb t0, t2(t1!)
+cv.lb t0, (t1), t2
+# CHECK-INSTR: cv.lb t0, (t1), t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x00]
 
-cv.lb a0, a2(a1!)
-# CHECK-INSTR: cv.lb a0, a2(a1!)
+cv.lb a0, (a1), a2
+# CHECK-INSTR: cv.lb a0, (a1), a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00]
 
 

diff --git a/llvm/test/MC/RISCV/corev/mem/lbu-invalid.s b/llvm/test/MC/RISCV/corev/mem/lbu-invalid.s
@@ -1,29 +1,32 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
-cv.lbu t0, 0(0!)
-# CHECK-ERROR: expected register
+cv.lbu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
 
-cv.lbu 0, 0(t1!)
+cv.lbu 0, (t1), 0
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lbu t0, 0(t1)
+cv.lbu 0, (0), t0 
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lbu t0, 2048(t1!)
+cv.lbu t0, (t1), -2049
 # CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lbu t0, t1(0!)
-# CHECK-ERROR: expected register
+cv.lbu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lbu 0, t1(t1!)
+cv.lbu t0, (0), t1
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lbu t0, t1(0)
-# CHECK-ERROR: expected register
-
-cv.lbu 0, 0(t1)
+cv.lbu 0, (t1), t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lbu t0
 # CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t2)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lbu t0, (t1), t2, t3 
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/mem/lbu.s b/llvm/test/MC/RISCV/corev/mem/lbu.s
@@ -1,22 +1,22 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
-cv.lbu t0, 0(t1!)
-# CHECK-INSTR: cv.lbu t0, 0(t1!)
+cv.lbu t0, (t1), 0
+# CHECK-INSTR: cv.lbu t0, (t1), 0
 # CHECK-ENCODING: [0x8b,0x42,0x03,0x00]
 
-cv.lbu a0, 2047(a1!)
-# CHECK-INSTR: cv.lbu a0, 2047(a1!)
+cv.lbu a0, (a1), 2047
+# CHECK-INSTR: cv.lbu a0, (a1), 2047
 # CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f]
 
 
 
-cv.lbu t0, t2(t1!)
-# CHECK-INSTR: cv.lbu t0, t2(t1!)
+cv.lbu t0, (t1), t2
+# CHECK-INSTR: cv.lbu t0, (t1), t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x10]
 
-cv.lbu a0, a2(a1!)
-# CHECK-INSTR: cv.lbu a0, a2(a1!)
+cv.lbu a0, (a1), a2
+# CHECK-INSTR: cv.lbu a0, (a1), a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10]
 
 

diff --git a/llvm/test/MC/RISCV/corev/mem/lh-invalid.s b/llvm/test/MC/RISCV/corev/mem/lh-invalid.s
@@ -1,29 +1,35 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
-cv.lh t0, 0(0!)
-# CHECK-ERROR: expected register
+cv.lh t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
 
-cv.lh 0, 0(t1!)
+cv.lh 0, (t1), 0
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lh t0, 0(t1)
+cv.lh 0, (0), t2
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lh t0, 2048(t1!)
+cv.lh t0, (t1), -2049
 # CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lh t0, t1(0!)
-# CHECK-ERROR: expected register
+cv.lh t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lh 0, t1(t1!)
+cv.lh t0, (0), t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lh t0, t1(0)
 # CHECK-ERROR: expected register
 
-cv.lh 0, 0(t1)
+cv.lh 0, (t1), t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lh t0
 # CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lh t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/mem/lh.s b/llvm/test/MC/RISCV/corev/mem/lh.s
@@ -1,22 +1,22 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
-cv.lh t0, 0(t1!)
-# CHECK-INSTR: cv.lh t0, 0(t1!)
+cv.lh t0, (t1), 0
+# CHECK-INSTR: cv.lh t0, (t1), 0
 # CHECK-ENCODING: [0x8b,0x12,0x03,0x00]
 
-cv.lh a0, 2047(a1!)
-# CHECK-INSTR: cv.lh a0, 2047(a1!)
+cv.lh a0, (a1), 2047
+# CHECK-INSTR: cv.lh a0, (a1), 2047
 # CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f]
 
 
 
-cv.lh t0, t2(t1!)
-# CHECK-INSTR: cv.lh t0, t2(t1!)
+cv.lh t0, (t1), t2
+# CHECK-INSTR: cv.lh t0, (t1), t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x02]
 
-cv.lh a0, a2(a1!)
-# CHECK-INSTR: cv.lh a0, a2(a1!)
+cv.lh a0, (a1), a2
+# CHECK-INSTR: cv.lh a0, (a1), a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02]
 
 

diff --git a/llvm/test/MC/RISCV/corev/mem/lhu-invalid.s b/llvm/test/MC/RISCV/corev/mem/lhu-invalid.s
@@ -1,29 +1,35 @@
 # RUN: not llvm-mc -triple=riscv32 --mattr=+xcvmem %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
 
-cv.lhu t0, 0(0!)
-# CHECK-ERROR: expected register
+cv.lhu t0, (0), 0
+# CHECK-ERROR: invalid operand for instruction
 
-cv.lhu 0, 0(t1!)
+cv.lhu 0, (t1), 0
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lhu t0, 0(t1)
+cv.lhu 0, 0(t1)
 # CHECK-ERROR: invalid operand for instruction
 
-cv.lhu t0, 2048(t1!)
+cv.lhu t0, (t1), -2049
 # CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lhu t0, t1(0!)
-# CHECK-ERROR: expected register
+cv.lhu t0, (t1), 2048
+# CHECK-ERROR: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047]
 
-cv.lhu 0, t1(t1!)
+cv.lhu t0, (0), t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lhu t0, t1(0)
 # CHECK-ERROR: expected register
 
-cv.lhu 0, 0(t1)
+cv.lhu 0, t0, t1
 # CHECK-ERROR: invalid operand for instruction
 
 cv.lhu t0
 # CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1)
+# CHECK-ERROR: too few operands for instruction
+
+cv.lhu t0, (t1), t2, t3
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/mem/lhu.s b/llvm/test/MC/RISCV/corev/mem/lhu.s
@@ -1,22 +1,22 @@
 # RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
 
-cv.lhu t0, 0(t1!)
-# CHECK-INSTR: cv.lhu t0, 0(t1!)
+cv.lhu t0, (t1), 0
+# CHECK-INSTR: cv.lhu t0, (t1), 0
 # CHECK-ENCODING: [0x8b,0x52,0x03,0x00]
 
-cv.lhu a0, 2047(a1!)
-# CHECK-INSTR: cv.lhu a0, 2047(a1!)
+cv.lhu a0, (a1), 2047
+# CHECK-INSTR: cv.lhu a0, (a1), 2047
 # CHECK-ENCODING: [0x0b,0xd5,0xf5,0x7f]
 
 
 
-cv.lhu t0, t2(t1!)
-# CHECK-INSTR: cv.lhu t0, t2(t1!)
+cv.lhu t0, (t1), t2
+# CHECK-INSTR: cv.lhu t0, (t1), t2
 # CHECK-ENCODING: [0xab,0x32,0x73,0x12]
 
-cv.lhu a0, a2(a1!)
-# CHECK-INSTR: cv.lhu a0, a2(a1!)
+cv.lhu a0, (a1), a2
+# CHECK-INSTR: cv.lhu a0, (a1), a2
 # CHECK-ENCODING: [0x2b,0xb5,0xc5,0x12]