[RISCV] Remove 'xcv' extension (#35)

The CORE-V ISA Extension Naming specification was recently updated. One of the consequences of this is that the option previously called 'xcorev' (but implemented as 'xcv' presently due to the prefix change) has been removed. However, the compiler does not presently reflect this change. This patch removes the 'xcv' march flag option so that the compiler and the CORE-V ISA Extension Naming specification match. See here for CORE-V ISA Extension Naming specification: (https://github.com/openhwgroup/core-v-sw/blob/master/specifications/corev-isa-extension-naming.md)
openhwgroup · Jun 9, 2023 · 8263119 · 8263119
1 parent 420c1e6
commit 8263119
Show file tree

Hide file tree

Showing 7 changed files with 0 additions and 4,418 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -480,17 +480,6 @@ def HasExtXcvelw
    : Predicate<"Subtarget->hasExtXcvelw()">,
               AssemblerPredicate<(any_of FeatureExtXcvelw),
               "'Xcvelw' (Event Load Word)">;
-// All CORE-V extensions
-def FeatureExtXcv
-    : SubtargetFeature<"xcv", "HasExtXcv", "true",
-                       "'Xcv' (CORE-V extensions)",
-                       [FeatureExtXcvhwlp, FeatureExtXcvmac,
-                        FeatureExtXcvalu, FeatureExtXcvsimd,
-                        FeatureExtXcvbitmanip, FeatureExtXcvmem,
-                        FeatureExtXcvbi,FeatureExtXcvelw]>;
-def HasExtXCoreV : Predicate<"Subtarget->hasExtXcv()">,
-                              AssemblerPredicate<(all_of FeatureExtXcv),
-                              "'Xcv' (CORE-V extensions)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;

diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -94,7 +94,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasRV32 = false;
   bool HasStdExtZvlsseg = false;
   bool HasStdExtZvamo = false;
-  bool HasExtXcv = false;
   bool HasExtXcvhwlp = false;
   bool HasExtXcvmac = false;
   bool HasExtXcvalu = false;
@@ -204,7 +203,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool hasStdExtZvamo() const { return HasStdExtZvamo; }
-  bool hasExtXcv() const { return HasExtXcv; }
   bool hasExtXcvhwlp() const { return HasExtXcvhwlp; }
   bool hasExtXcvmac() const { return HasExtXcvmac; }
   bool hasExtXcvalu() const { return HasExtXcvalu; }

diff --git a/llvm/test/MC/RISCV/corev/alu-all-extensions.s b/llvm/test/MC/RISCV/corev/alu-all-extensions.s
diff --git a/llvm/test/MC/RISCV/corev/hwlp-all-extensions.s b/llvm/test/MC/RISCV/corev/hwlp-all-extensions.s
diff --git a/llvm/test/MC/RISCV/corev/mac-all-extensions.s b/llvm/test/MC/RISCV/corev/mac-all-extensions.s