[RISCV][Clang] Implement XcvElw Clang Builtins

openhwgroup · Dec 12, 2023 · 4535d99 · 4535d99
1 parent 48d6907
commit 4535d99
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Showing 3 changed files with 23 additions and 3 deletions.
diff --git a/clang/include/clang/Basic/BuiltinsRISCVCOREV.def b/clang/include/clang/Basic/BuiltinsRISCVCOREV.def
@@ -218,6 +218,8 @@ TARGET_BUILTIN(alu_subuN, "UZiUZiUZiUc", "nc", "xcvalu")
 TARGET_BUILTIN(alu_subRN, "ZiZiZiUc", "nc", "xcvalu")
 TARGET_BUILTIN(alu_subuRN, "UZiUZiUZiUc", "nc", "xcvalu")
 
+TARGET_BUILTIN(elw_elw, "iv*", "nc", "xcvelw")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
 #undef PSEUDO_BUILTIN
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -19363,12 +19363,13 @@ static Value *EmitCoreVIntrinsic(CodeGenFunction &CGF, unsigned BuiltinID,
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
     if (Ops[i]->getType() != MachineType) {
       QualType type = E->getArg(i)->getType();
-      assert((type->isSignedIntegerType() || type->isUnsignedIntegerType()) &&
+      assert((type->isSignedIntegerType() || type->isUnsignedIntegerType() ||
+          type->isPointerType()) &&
              "Argument of Core-V builtin must have signed or unsigned integer "
-             "type");
+             "or Pointer type");
       if (type->isSignedIntegerType()) {
         Ops[i] = CGF.Builder.CreateSExt(Ops[i], MachineType);
-      } else {
+      } else if ((type->isUnsignedIntegerType())) {
         Ops[i] = CGF.Builder.CreateZExt(Ops[i], MachineType);
       }
     }

diff --git a/clang/test/CodeGen/RISCV/corev-intrinsics/elw.c b/clang/test/CodeGen/RISCV/corev-intrinsics/elw.c
@@ -0,0 +1,17 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv32 -target-feature +xcvelw -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+
+// CHECK-LABEL: @test_elw(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-NEXT:    store ptr [[B:%.*]], ptr [[B_ADDR]], align 4
+// CHECK-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
+// CHECK-NEXT:    [[ADD_PTR:%.*]] = getelementptr i8, ptr [[TMP0]], i32 8
+// CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.cv.elw.elw(ptr [[ADD_PTR]])
+// CHECK-NEXT:    ret i32 [[TMP1]]
+//
+int test_elw(void *b) {
+  return __builtin_riscv_cv_elw_elw(b + 8);
+}