Skip to content

Commit

Permalink
Merge pull request #2392 from XavierAubert/cv32e40p/dev_dd_w12a
Browse files Browse the repository at this point in the history 
CV32E40Pv2 Verification update w12
  • Loading branch information
@MikeOpenHWGroup
MikeOpenHWGroup authored Mar 21, 2024
2 parents 4aeed1e + 4a14542 commit fe5a3a7
Show file tree
Hide file tree
Showing 23 changed files with 2,625 additions and 531 deletions.
142 changes: 88 additions & 54 deletions cv32e40p/env/uvme/cov/uvme_cv32e40p_fp_instr_covg.sv
View file

Large diffs are not rendered by default.

189 changes: 138 additions & 51 deletions cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv
View file

Large diffs are not rendered by default.

8 changes: 5 additions & 3 deletions cv32e40p/env/uvme/cov/uvme_rv32x_hwloop_covg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -788,7 +788,7 @@ class uvme_rv32x_hwloop_covg # (
endfunction : check_ebreakm_entry

function void check_exception_exit();
if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET) begin
if (cv32e40p_rvvi_vif.valid && cv32e40p_rvvi_vif.insn == TB_INSTR_MRET && !cv32e40p_rvvi_vif.trap) begin
is_ebreak = 0; is_ecall = 0; is_illegal = 0; is_trap = 0;
`uvm_info(_header, $sformatf("DEBUG - EXCEPTION Exit"), UVM_DEBUG);
end
Expand Down Expand Up @@ -880,7 +880,7 @@ class uvme_rv32x_hwloop_covg # (
discarded_insn = insn_list_in_hwloop_main[j].pop_back();
assert(discarded_insn == INSN_EBREAKM);
void'(hwloop_evt_loc_main[j][DBG_EBREAKM].pop_back());
hwloop_stat_main.track_lp_cnt[j]++; lpend_has_pending_irq_main[j] = 0;
hwloop_stat_main.track_lp_cnt[j]++; lpend_has_pending_irq_main[j] = 0;
end
end // for
end
Expand Down Expand Up @@ -986,6 +986,8 @@ class uvme_rv32x_hwloop_covg # (
`IF_CURRENT_IS_MAIN_HWLOOP(1, IS_IRQ)
update_prev_irq_onehot_priority();
`uvm_info(_header, $sformatf("DEBUG - IRQ Entry"), UVM_DEBUG);
if (lpend_has_pending_irq_main[0]) begin hwloop_stat_main.track_lp_cnt[0]++; lpend_has_pending_irq_main[0] = 0; end
if (lpend_has_pending_irq_main[1]) begin hwloop_stat_main.track_lp_cnt[1]++; lpend_has_pending_irq_main[1] = 0; end
is_irq = 1; wait (!is_irq); continue;
end
end // IRQ_ENTRY
Expand Down Expand Up @@ -1021,7 +1023,7 @@ class uvme_rv32x_hwloop_covg # (
`uvm_info(_header, $sformatf("DEBUG - No prematured hwloops when test done"), UVM_DEBUG);
end
else begin
`uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... ")); // fixme: to be commented out
`uvm_error(_header, $sformatf("Detected prematured hwloops when test done. Please debug ... "));
end
endfunction : final_phase

Expand Down
40 changes: 36 additions & 4 deletions cv32e40p/env/uvme/uvme_cv32e40p_macros.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,13 @@
`define APU_INSTR_WITH_NO_FD \
APU_OP_FCMP, APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_F2I_U

`define RV32_INSTR_WITH_NO_RS2 \
TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM
// LIST1 is CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F
`define RV32_OPCODE_LIST1_WITH_RD \
TB_OPCODE_OP, TB_OPCODE_OPIMM, TB_OPCODE_LOAD, TB_OPCODE_JALR, TB_OPCODE_JAL, TB_OPCODE_AUIPC, TB_OPCODE_LUI, \
OPCODE_CUSTOM_0, OPCODE_CUSTOM_1, OPCODE_CUSTOM_2, OPCODE_CUSTOM_3

`define RV32_OPCODE_WITH_NO_RS2 \
TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM

`define RV32F_INSTR_WITH_FS1 \
TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, TB_INS_FSQRT, \
Expand All @@ -43,6 +48,13 @@
`define RV32F_INSTR_WITH_FS3 \
TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB

`define RV32F_INSTR_WITH_RS1 \
TB_INS_FLW, TB_INS_FSW, TB_INS_FMVSX, TB_INS_FCVTSW, TB_INS_FCVTSWU

// `define RV32ZFINX_INSTR_W_RS1 `RV32F_INSTR_WITH_FS1
`define RV32ZFINX_INSTR_W_RS2 `RV32F_INSTR_WITH_FS2
`define RV32ZFINX_INSTR_W_RS3 `RV32F_INSTR_WITH_FS3

`define RV32F_OP_WITHOUT_FDIV_FSQRT \
APU_OP_FMADD, APU_OP_FNMSUB, APU_OP_FADD, APU_OP_FMUL, APU_OP_FSGNJ, APU_OP_FMINMAX, APU_OP_FCMP, \
APU_OP_FCLASSIFY, APU_OP_F2I, APU_OP_I2F, APU_OP_FMSUB, APU_OP_FNMADD, APU_OP_FSUB, APU_OP_FSGNJ_SE, \
Expand All @@ -61,14 +73,14 @@
wildcard bins fmax = {TB_INS_FMAX}; \
wildcard bins fcvtws = {TB_INS_FCVTWS}; \
wildcard bins fcvtwus = {TB_INS_FCVTWUS}; \
wildcard bins fmvxs = {TB_INS_FMVXS}; \
wildcard bins fmvxw = {TB_INS_FMVXS}; \
wildcard bins feqs = {TB_INS_FEQS}; \
wildcard bins flts = {TB_INS_FLTS}; \
wildcard bins fles = {TB_INS_FLES}; \
wildcard bins fclass = {TB_INS_FCLASS}; \
wildcard bins fcvtsw = {TB_INS_FCVTSW}; \
wildcard bins fcvtswu = {TB_INS_FCVTSWU}; \
wildcard bins fmvsw = {TB_INS_FMVSX}; \
wildcard bins fmvwx = {TB_INS_FMVSX}; \
wildcard bins fmadd = {TB_INS_FMADD}; \
wildcard bins fmsub = {TB_INS_FMSUB}; \
wildcard bins fnmsub = {TB_INS_FNMSUB}; \
Expand Down Expand Up @@ -234,6 +246,7 @@
// bins apu_op_fsgnj_se = {APU_OP_FSGNJ_SE}; \ exclude this from macro because it is fmv for RV32F
// bins apu_op_f2f = {APU_OP_F2F}; \ exclude this from above macro because it is for RV32D

// cv32e40p opcode (exclude compress and f-compress)
`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC \
bins system_opcode = {TB_OPCODE_SYSTEM}; \
bins fence_opcode = {TB_OPCODE_FENCE}; \
Expand All @@ -258,6 +271,7 @@
bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \
bins xpulp_custom_3 = {OPCODE_CUSTOM_3};

// cv32e40p opcode (exclude compress, f-compress, f-load/store)
`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_FPLS \
bins system_opcode = {TB_OPCODE_SYSTEM}; \
bins fence_opcode = {TB_OPCODE_FENCE}; \
Expand All @@ -280,6 +294,24 @@
bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \
bins xpulp_custom_3 = {OPCODE_CUSTOM_3};

// cv32e40p opcode (exclude compress, f-compress and f)
`define CV32E40P_INSTR_OPCODE_BIT_6_0_BINS__NO_RV32C_FC_F \
bins system_opcode = {TB_OPCODE_SYSTEM}; \
bins fence_opcode = {TB_OPCODE_FENCE}; \
bins op_opcode = {TB_OPCODE_OP}; \
bins opimm_opcode = {TB_OPCODE_OPIMM}; \
bins store_opcode = {TB_OPCODE_STORE}; \
bins load_opcode = {TB_OPCODE_LOAD}; \
bins branch_opcode = {TB_OPCODE_BRANCH}; \
bins jalr_opcode = {TB_OPCODE_JALR}; \
bins jal_opcode = {TB_OPCODE_JAL}; \
bins auipc_opcode = {TB_OPCODE_AUIPC}; \
bins lui_opcode = {TB_OPCODE_LUI}; \
bins xpulp_custom_0 = {OPCODE_CUSTOM_0}; \
bins xpulp_custom_1 = {OPCODE_CUSTOM_1}; \
bins xpulp_custom_2 = {OPCODE_CUSTOM_2}; \
bins xpulp_custom_3 = {OPCODE_CUSTOM_3};

`define RV32X_PULP_INSTR_BINS \
wildcard bins cv_lb_pi_ri = {INSTR_CV_LB_PI_RI}; \
wildcard bins cv_lh_pi_ri = {INSTR_CV_LH_PI_RI}; \
Expand Down
1 change: 1 addition & 0 deletions cv32e40p/regress/cv32e40pv2_for_func_cvg_improvement.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ tests:
description: This test is to improve func coverage holes in uvme_interrupt_covg_v2
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_directed_for_interrupt_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
skip_sim: pulp
num: 5

corev_directed_for_hwloop_covg_test:
Expand Down
44 changes: 44 additions & 0 deletions cv32e40p/regress/cv32e40pv2_interrupt_debug_short.yaml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -437,3 +437,47 @@ tests:
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=riscv_ebreak_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=20000000"
num: 1


# fixme: temporary park here for regression purpose. need to reloacate again once below tests are stable
corev_directed_for_interrupt_covg_test:
build: uvmt_cv32e40p
description: This test is to improve func coverage holes in uvme_interrupt_covg_v2
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_directed_for_interrupt_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"
skip_sim: pulp
num: 5

corev_directed_for_hwloop_covg_test:
description: This test is to improve func coverage holes in uvme_rv32x_hwloop_covg
build: uvmt_cv32e40p
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test TEST=corev_directed_for_hwloop_covg_test CFG_PLUSARGS="+UVM_TIMEOUT=60000000"
num: 5

corev_directed_fp_mulcyc_interleave_illegal_test_with_int_and_debug:
testname: corev_rand_fp_instr_debug
description: This test is to improve func coverage holes in uvme_debug_covg
build: uvmt_cv32e40p
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000" VSIM_USER_FLAGS=+add_b2b_illegal_insn
test_cfg: gen_rand_int
skip_sim: pulp
num: 1

corev_directed_fp_mulcyc_test_with_int_and_debug:
testname: corev_rand_fp_instr_debug
description: This test is to improve func coverage holes in uvme_debug_covg
build: uvmt_cv32e40p
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test TEST=corev_rand_fp_instr_debug CFG_PLUSARGS="+UVM_TIMEOUT=40000000"
test_cfg: gen_rand_int
skip_sim: pulp
num: 5

debug_test_trigger:
build: uvmt_cv32e40p
description: This custom legacy test is needed to improve func coverage holes in uvme_debug_covg
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=debug_test_trigger
num: 1
209 changes: 209 additions & 0 deletions cv32e40p/regress/cv32e40pv2_legacy_v1.yaml
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,209 @@
name: cv32e40pv2_legacy_v1
description: regression for CV32E40Pv2, containing all tests not in any of other v2 files, which focus mainly on legacy

# List of builds
builds:
clean_fw:
cmd: make clean-bsp clean_test_programs
dir: cv32e40p/sim/uvmt
clean_corev-dv:
cmd: make clean_riscv-dv clone_riscv-dv
dir: cv32e40p/sim/uvmt
uvmt_cv32e40p:
cmd: make comp comp_corev-dv
dir: cv32e40p/sim/uvmt
cfg: pulp

# List of tests
tests:
###################################################################################################
############ START List of tests that are not in any of the 4 files mentionned above

hello-world:
build: uvmt_cv32e40p
description: world
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=hello-world CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_arithmetic_base_test:
build: uvmt_cv32e40p
description: corev_rand_arithmetic_base_test
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_arithmetic_base_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_illegal_instr_test:
build: uvmt_cv32e40p
description: corev_rand_illegal_instr_test
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_illegal_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_instr_long_stall:
build: uvmt_cv32e40p
description: corev_rand_instr_long_stall
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_long_stall CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_instr_test:
build: uvmt_cv32e40p
description: corev_rand_instr_test
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

corev_rand_jump_stress_test:
build: uvmt_cv32e40p
description: corev_rand_jump_stress_test
dir: cv32e40p/sim/uvmt
cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_jump_stress_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

all_csr_por:
build: uvmt_cv32e40p
description: all_csr_por
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=all_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=300000000"

branch_zero:
build: uvmt_cv32e40p
description: branch_zero
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=branch_zero CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

csr_instr_asm:
build: uvmt_cv32e40p
description: csr_instr_asm
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=csr_instr_asm CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

coremark:
build: uvmt_cv32e40p
description: coremark
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=coremark CFG_PLUSARGS="+UVM_TIMEOUT=3000000000"

cv32e40p_readonly_csr_access_test:
build: uvmt_cv32e40p
description: cv32e40p_readonly_csr_access_test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=cv32e40p_readonly_csr_access_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

debug_test_trigger:
build: uvmt_cv32e40p
description: debug_test_trigger
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=debug_test_trigger CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

dhrystone:
build: uvmt_cv32e40p
description: dhrystone
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=dhrystone CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

fibonacci:
build: uvmt_cv32e40p
description: fibonacci
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=fibonacci CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

generic_exception_test:
build: uvmt_cv32e40p
description: generic_exception_test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=generic_exception_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

hpmcounter_basic_test:
build: uvmt_cv32e40p
description: hpmcounter_basic_test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=hpmcounter_basic_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

hpmcounter_hazard_test:
build: uvmt_cv32e40p
description: hpmcounter_hazard_test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=hpmcounter_hazard_test CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

illegal:
build: uvmt_cv32e40p
description: illegal
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=illegal CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

illegal_instr_test:
build: uvmt_cv32e40p
description: illegal_instr_test
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=illegal_instr_test CFG_PLUSARGS="+UVM_TIMEOUT=3000000000"

isa_fcov_holes:
build: uvmt_cv32e40p
description: isa_fcov_holes
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=isa_fcov_holes CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

load_store_rs1_zero:
build: uvmt_cv32e40p
description: load_store_rs1_zero
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=load_store_rs1_zero CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

matmul_32b_float:
build: uvmt_cv32e40p
description: matmul_32b_float
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=matmul_32b_float CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

matmul_32b_int:
build: uvmt_cv32e40p
description: matmul_32b_int
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=matmul_32b_int CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

mhpmcounter29_csr_access_test_1:
build: uvmt_cv32e40p
description: mhpmcounter29_csr_access_test_1
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

mhpmcounter29_csr_access_test_2:
build: uvmt_cv32e40p
description: mhpmcounter29_csr_access_test_2
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=mhpmcounter29_csr_access_test_2 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

misalign:
build: uvmt_cv32e40p
description: misalign
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=misalign CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

modeled_csr_por:
build: uvmt_cv32e40p
description: modeled_csr_por
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=modeled_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

perf_counters_instructions:
build: uvmt_cv32e40p
description: perf_counters_instructions
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=perf_counters_instructions CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

requested_csr_por:
build: uvmt_cv32e40p
description: requested_csr_por
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=requested_csr_por CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

riscv_arithmetic_basic_test_0:
build: uvmt_cv32e40p
description: riscv_arithmetic_basic_test_0
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_0 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

riscv_arithmetic_basic_test_1:
build: uvmt_cv32e40p
description: riscv_arithmetic_basic_test_1
dir: cv32e40p/sim/uvmt
cmd: make test COREV=YES TEST=riscv_arithmetic_basic_test_1 CFG_PLUSARGS="+UVM_TIMEOUT=30000000"

############ END List of tests that are not in any of the v2 regress list
###################################################################################################
Loading

0 comments on commit fe5a3a7

Please sign in to comment.