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Merge pull request #2369 from XavierAubert/cv32e40p/dev_dd_w7
CV32E40Pv2 Verification update
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/* Script for -z combreloc */ | ||
/* Copyright (C) 2014-2020 Free Software Foundation, Inc. | ||
Copyright (C) 2019 ETH Zürich and University of Bologna | ||
Copyright (C) 2020 OpenHW Group | ||
Copying and distribution of this script, with or without modification, | ||
are permitted in any medium without royalty provided the copyright | ||
notice and this notice are preserved. */ | ||
|
||
/* This linker script is adapted from the default linker script for upstream | ||
RISC-V GCC. It has been modified for use in verification of CORE-V cores. | ||
*/ | ||
|
||
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv", | ||
"elf32-littleriscv") | ||
OUTPUT_ARCH(riscv) | ||
ENTRY(_start) | ||
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/* CORE-V */ | ||
MEMORY | ||
{ | ||
/* Our testbench is a bit weird in that we initialize the RAM (thus | ||
allowing initialized sections to be placed there). Infact we dump all | ||
sections to ram. */ | ||
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ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000 | ||
dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000 | ||
} | ||
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SECTIONS | ||
{ | ||
/* CORE-V Debugger Code: This section address must be the same as the | ||
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/* CORE-V: we want a fixed entry point */ | ||
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