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Merge pull request #2369 from XavierAubert/cv32e40p/dev_dd_w7
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CV32E40Pv2 Verification update
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MikeOpenHWGroup authored Feb 19, 2024
2 parents 7173b54 + aedcc23 commit 65fb814
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Showing 69 changed files with 35,169 additions and 132 deletions.
6 changes: 6 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -66,3 +66,9 @@ transcript
.opt-rtl
tools/spike
tools/verilator*
VRMDATA
*fir_q31*
*float32_division_test*
*whetstone*
*.do
*eembc*
21 changes: 15 additions & 6 deletions bin/cv_regress
Original file line number Diff line number Diff line change
Expand Up @@ -184,12 +184,6 @@ def read_file(args, file, f_idx=0):
test.num = int(args.num[0])
else:
test.num = 1
elif test.num != 1:
if args.num:
try:
test.num = int(args.num[f_idx])
except IndexError:
test.num = int(args.num[0])

try:
if test.simulator in t['skip_sim']:
Expand All @@ -200,9 +194,24 @@ def read_file(args, file, f_idx=0):
continue
except KeyError:
pass
except AttributeError as ex:
# no simulator or cfg in test Object, need to check build parameter, and remove the build
# from test build list before adding the test to the regress list
if ex.args[0].find('cfg') > 0:
new_list_of_builds = [b for b in test.builds if regression.builds[b].cfg not in t['skip_sim']]
logger.info('Regression: builds {} have been removed for test {} due to cfg skipped'.format([b for b in test.builds if b not in new_list_of_builds], test.name))
test.builds = new_list_of_builds

if not test.builds:
logger.warning('Regression: Test {} has no build and will be skipped'.format(test.name))
continue

regression.add_test(test)

if not regression.tests:
logger.fatal('Regression: No test in the regression {}'.format(regression.name))
os.sys.exit(2)

return regression

# Defaults and globals
Expand Down
17 changes: 16 additions & 1 deletion cv32e40p/bsp/link.ld
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,7 @@ SECTIONS
{
KEEP(*(.debugger));
} >dbg
.debugger_exception (0x1A111000):
.debugger_exception (0x1A111600):
{
KEEP(*(.debugger_exception));
} >dbg
Expand Down Expand Up @@ -242,8 +242,23 @@ SECTIONS
. = SEGMENT_START("ldata-segment", .);
. = ALIGN(32 / 8);
__bss_end = .;
/* In toolchain, x3 is the gp global pointer register and gp relaxation occurs.
When GP relaxation is enabled, gp should be initialized at startup to __global_pointer$ and
the rest of the code should not modify gp.
If you want to disable GP relaxation, then set __global_pointer$ to linker file or remove it completely.
In corev-dv random generator test, gp (x3) is used as any register and can be written many times.
And it is using la pseudo-instruction which is replaced by auipc/addi which can be gp relaxed,
meaning auipc will be omitted after being executed once in crt0.S. Then final binary is not functional.

https://github.com/openhwgroup/corev-gcc/issues/92

Following lines will be kept in a new linker file (link_gp_relax.ld) used for benchmarks and applications
as gp relaxation generally improves code size and performances.

__global_pointer$ = MIN(__SDATA_BEGIN__ + 0x800,
MAX(__DATA_BEGIN__ + 0x800, __bss_end - 0x800));
*/
__global_pointer$ = 0;
_end = .; PROVIDE (end = .);
. = DATA_SEGMENT_END (.);

Expand Down
311 changes: 311 additions & 0 deletions cv32e40p/bsp/link_gp_relax.ld
Original file line number Diff line number Diff line change
@@ -0,0 +1,311 @@
/* Script for -z combreloc */
/* Copyright (C) 2014-2020 Free Software Foundation, Inc.
Copyright (C) 2019 ETH Zürich and University of Bologna
Copyright (C) 2020 OpenHW Group
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */

/* This linker script is adapted from the default linker script for upstream
RISC-V GCC. It has been modified for use in verification of CORE-V cores.
*/

OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
"elf32-littleriscv")
OUTPUT_ARCH(riscv)
ENTRY(_start)

/* CORE-V */
MEMORY
{
/* Our testbench is a bit weird in that we initialize the RAM (thus
allowing initialized sections to be placed there). Infact we dump all
sections to ram. */

ram (rwxai) : ORIGIN = 0x00000000, LENGTH = 0x400000
dbg (rwxai) : ORIGIN = 0x1A110800, LENGTH = 0x1000
}

SECTIONS
{
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KEEP(*(.debugger_exception));
} >dbg
/* Debugger Stack*/
.debugger_stack : ALIGN(16)
{
PROVIDE(__debugger_stack_start = .);
. = 0x80;
} >dbg

/* CORE-V: we want a fixed entry point */
PROVIDE(__boot_address = 0x80);

/* CORE-V: interrupt vectors */
.vectors (ORIGIN(ram)):
{
PROVIDE(__vector_start = .);
KEEP(*(.vectors));
} >ram

/* CORE-V: crt0 init code */
.init (__boot_address):
{
KEEP (*(SORT_NONE(.init)))
KEEP (*(.text.start))
} >ram

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/* These sections are generated by the Sun/Oracle C++ compiler. */
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/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. */
. = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
/* Exception handling */
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) *(.eh_frame.*) } >ram
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/* Thread Local Storage sections */
.tdata :
{
PROVIDE_HIDDEN (__tdata_start = .);
*(.tdata .tdata.* .gnu.linkonce.td.*)
} >ram
.tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >ram
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >ram
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >ram
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >ram
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >ram
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >ram
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.data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) }
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. = DATA_SEGMENT_RELRO_END (0, .);
.data :
{
__DATA_BEGIN__ = .;
*(.data .data.* .gnu.linkonce.d.*)
SORT(CONSTRUCTORS)
} >ram
.data1 : { *(.data1) } >ram
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/* We want the small data sections together, so single-instruction offsets
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we can shorten the on-disk segment size. */
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{
__SDATA_BEGIN__ = .;
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
} >ram
_edata = .; PROVIDE (edata = .);
. = .;
__bss_start = .;
.sbss :
{
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
} >ram
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{
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*(COMMON)
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
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FIXME: Why do we need it? When there is no .bss section, we do not
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. = ALIGN(. != 0 ? 32 / 8 : 1);
} >ram
. = ALIGN(32 / 8);
. = SEGMENT_START("ldata-segment", .);
. = ALIGN(32 / 8);
__bss_end = .;
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/* Heap grows upward towards end of ram */
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PROVIDE(__heap_start = .);
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/* Stack grows downward from end of ram */
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}

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