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fix(project): minor changes for better compatibility with newer pocke…
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…t variants

- change seed and assignments
- fix issue template
- change category to arcade-multi
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@boogermann
boogermann committed Apr 23, 2024
1 parent 8af783f commit 2552f52
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2 changes: 1 addition & 1 deletion .github/ISSUE_TEMPLATE/BUG_REPORT.yml
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Expand Up @@ -17,7 +17,7 @@ body:
Hi there,
Thank you for opening an issue. Please note that we try to keep the issue tracker reserved for bug reports.
Make sure to [search for existing issues](https://github.com/opengateware/arcade-galivan/issues?q=label%3Abug) before filing a new one!
Make sure to [search for existing issues](https://github.com/opengateware/arcade-irem_m92/issues?q=label%3Abug) before filing a new one!
- type: input
id: version
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4 changes: 2 additions & 2 deletions .github/ISSUE_TEMPLATE/QUESTION.yml
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Expand Up @@ -17,12 +17,12 @@ body:
Hi there,
Please note that we try to keep the issue tracker reserved for bug reports.
Make sure to [search for existing questions](https://github.com/opengateware/arcade-galivan/issues?q=label%3Aquestion) before filing a new one!
Make sure to [search for existing questions](https://github.com/opengateware/arcade-irem_m92/issues?q=label%3Aquestion) before filing a new one!
- type: textarea
id: question
attributes:
label: Ask a question about Cosmo Police Galivan Compatible Gateware IP Core
label: Ask a question about Irem M92 Compatible Gateware IP Core
placeholder: |
Ask your question here! Please keep the questions related to the FPGA Core only.
validations:
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2 changes: 1 addition & 1 deletion pkg/pocket/Platforms/irem_m92.json
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@@ -1,6 +1,6 @@
{
"platform": {
"category": "Arcade",
"category": "Arcade Multi",
"name": "Irem M92",
"manufacturer": "Irem",
"year": 1991
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14 changes: 7 additions & 7 deletions projects/irem_m92_pocket.qsf
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Expand Up @@ -21,14 +21,14 @@ set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SEED 1
set_global_assignment -name SEED 2

# ==============================================================================
# Analysis & Synthesis Assignments
# ==============================================================================
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
#set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
Expand Down Expand Up @@ -78,12 +78,12 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name AUTO_RESOURCE_SHARING ON

set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION NEVER
#set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
#set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION NEVER
#set_global_assignment -name FITTER_EFFORT "FAST FIT"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name MUX_RESTRUCTURE ON
#set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
#set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
#set_global_assignment -name MUX_RESTRUCTURE ON
# ==============================================================================
# Incremental Compilation Assignments
# ==============================================================================
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96 changes: 48 additions & 48 deletions target/pocket/core_top.sv
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Expand Up @@ -911,54 +911,54 @@ module core_top
wire hs_access_write;
wire hs_configured;

hiscore_io #(
// HiScore NVRAM
.HS_AW ( HS_AW ), // [p]
.HS_SW ( HS_SW ), // [p]
.HS_CFG_AW ( HS_CFG_AW ), // [p]
.HS_CFG_LW ( HS_CFG_LW ), // [p]
.HS_CONFIG ( HS_CONFIG ), // [p]
.HS_DATA ( HS_DATA ), // [p]
// MPU <-> FPGA (Data I/O)
.HS_MASK ( HS_MASK ), // [p]
.HS_WR_DELAY ( HS_WR_DELAY ), // [p]
.HS_WR_HOLD ( HS_WR_HOLD ), // [p]
.HS_RD_DELAY ( HS_RD_DELAY ) // [p]
) u_pocket_hiscore_io (
.clk_74a ( clk_74a ), // [i]
.clk_memory ( clk_sys ), // [i]
.pll_core_locked ( pll_core_locked_s ), // [i]
.reset_sw ( reset_sw ), // [i]
.pause_core ( pause_core ), // [i]
// Bridge Data Slots
.dataslot_requestwrite ( dataslot_requestwrite ), // [i]
.dataslot_requestwrite_id ( dataslot_requestwrite_id ), // [i]
.dataslot_requestread ( dataslot_requestread ), // [i]
.dataslot_requestread_id ( dataslot_requestread_id ), // [i]
.dataslot_allcomplete ( dataslot_allcomplete ), // [i]
// Bridge Write/Read to/From FPGA)
.bridge_endian_little ( bridge_endian_little ), // [i]
.bridge_addr ( bridge_addr ), // [i]
.bridge_wr ( bridge_wr ), // [i]
.bridge_wr_data ( bridge_wr_data ), // [i]
.bridge_rd ( bridge_rd ), // [i]
.bridge_rd_data ( nvm_bridge_rd_data ), // [o]
// Pocket Bridge Data Tables
.datatable_addr ( datatable_addr ), // [o]
.datatable_wren ( datatable_wren ), // [o]
.datatable_data ( datatable_data ), // [o]
// HiScore NVRAM Size
.nvram_size ( nvram_size ), // [i] Number of bytes required for Save
// HiScore Interface
.hs_write_en ( hs_write_en ), // [o] Write to game RAM (active high)
.hs_address ( hs_address ), // [o] Address in game RAM to read/write score data
.hs_data_in ( hs_data_in ), // [o] Data to send to game RAM
.hs_data_out ( hs_data_out ), // [i] Incoming data from game RAM
.hs_access_read ( hs_access_read ), // [o]
.hs_access_write ( hs_access_write ), // [o]
.hs_configured ( hs_configured ), // [o]
.hs_pause ( pause_req ) // [o] Pause core CPU to prepare for/relax after RAM access
);
// hiscore_io #(
// // HiScore NVRAM
// .HS_AW ( HS_AW ), // [p]
// .HS_SW ( HS_SW ), // [p]
// .HS_CFG_AW ( HS_CFG_AW ), // [p]
// .HS_CFG_LW ( HS_CFG_LW ), // [p]
// .HS_CONFIG ( HS_CONFIG ), // [p]
// .HS_DATA ( HS_DATA ), // [p]
// // MPU <-> FPGA (Data I/O)
// .HS_MASK ( HS_MASK ), // [p]
// .HS_WR_DELAY ( HS_WR_DELAY ), // [p]
// .HS_WR_HOLD ( HS_WR_HOLD ), // [p]
// .HS_RD_DELAY ( HS_RD_DELAY ) // [p]
// ) u_pocket_hiscore_io (
// .clk_74a ( clk_74a ), // [i]
// .clk_memory ( clk_sys ), // [i]
// .pll_core_locked ( pll_core_locked_s ), // [i]
// .reset_sw ( reset_sw ), // [i]
// .pause_core ( pause_core ), // [i]
// // Bridge Data Slots
// .dataslot_requestwrite ( dataslot_requestwrite ), // [i]
// .dataslot_requestwrite_id ( dataslot_requestwrite_id ), // [i]
// .dataslot_requestread ( dataslot_requestread ), // [i]
// .dataslot_requestread_id ( dataslot_requestread_id ), // [i]
// .dataslot_allcomplete ( dataslot_allcomplete ), // [i]
// // Bridge Write/Read to/From FPGA)
// .bridge_endian_little ( bridge_endian_little ), // [i]
// .bridge_addr ( bridge_addr ), // [i]
// .bridge_wr ( bridge_wr ), // [i]
// .bridge_wr_data ( bridge_wr_data ), // [i]
// .bridge_rd ( bridge_rd ), // [i]
// .bridge_rd_data ( nvm_bridge_rd_data ), // [o]
// // Pocket Bridge Data Tables
// .datatable_addr ( datatable_addr ), // [o]
// .datatable_wren ( datatable_wren ), // [o]
// .datatable_data ( datatable_data ), // [o]
// // HiScore NVRAM Size
// .nvram_size ( nvram_size ), // [i] Number of bytes required for Save
// // HiScore Interface
// .hs_write_en ( hs_write_en ), // [o] Write to game RAM (active high)
// .hs_address ( hs_address ), // [o] Address in game RAM to read/write score data
// .hs_data_in ( hs_data_in ), // [o] Data to send to game RAM
// .hs_data_out ( hs_data_out ), // [i] Incoming data from game RAM
// .hs_access_read ( hs_access_read ), // [o]
// .hs_access_write ( hs_access_write ), // [o]
// .hs_configured ( hs_configured ), // [o]
// .hs_pause ( pause_req ) // [o] Pause core CPU to prepare for/relax after RAM access
// );

//! ------------------------------------------------------------------------
//! Clocks
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