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Add fdiv/fsqrt capability to rtl #57

Merged
merged 2 commits into from
Nov 3, 2023
Merged

Add fdiv/fsqrt capability to rtl #57

merged 2 commits into from
Nov 3, 2023

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nazavode
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@nazavode nazavode commented Nov 2, 2023

This PR adds a the ability to execute fdiv.* and fsqrt.* instructions in the Verilator model.

Note: waiting for this to be merged and the CI to pass to tag 2.4 as latest.

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github-actions bot commented Nov 2, 2023

kernel size version cycles
relu 16x16xf64 baseline.x 1339
relu 16x16xf64 ssr.x 846
relu 16x16xf64 ssr_frep_unroll.x 334
relu 16x16xf64 linalg.x 1337
relu 16x16xf64 ssr_frep.x 327
dsum 8x16xf32 baseline.x 1202
dsum 8x16xf32 ssr2d.x 273
dsum 8x16xf32 ssr1d_frep1d.x 187
dsum 8x16xf32 scf.x 3143
dsum 8x16xf32 ssr1d.x 253
dsum 8x16xf32 linalg.x 1089
dsum 8x16xf32 noalias.x 1202
matmul 8x8xf64 baseline.x 4230
matmul 8x8xf64 linalg.x 6214

@nazavode
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nazavode commented Nov 3, 2023

Addition of the div unit didn't alter cycle counts for all the existing kernels.

@compor
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compor commented Nov 3, 2023

Thanks! This is good news

@compor compor merged commit 153d8bd into main Nov 3, 2023
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@compor compor deleted the nazavode/fdiv-rtl branch November 3, 2023 09:58
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github-actions bot commented Nov 3, 2023

kernel size version cycles
relu 16x16xf64 baseline.x 1339
relu 16x16xf64 ssr.x 846
relu 16x16xf64 ssr_frep_unroll.x 334
relu 16x16xf64 linalg.x 1337
relu 16x16xf64 ssr_frep.x 327
dsum 8x16xf32 baseline.x 1202
dsum 8x16xf32 ssr2d.x 273
dsum 8x16xf32 ssr1d_frep1d.x 187
dsum 8x16xf32 scf.x 3143
dsum 8x16xf32 ssr1d.x 253
dsum 8x16xf32 linalg.x 1089
dsum 8x16xf32 noalias.x 1202
matmul 8x8xf64 baseline.x 4230
matmul 8x8xf64 linalg.x 6214

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2 participants