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clang: Switch 32bit register to register opcode to alternative
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03f1           add esi, ecx
2bf3           sub esi, ebx
0ac8           or  cl, al
23cd           and ecx, ebp
3ac3           cmp al, bl
32d0           xor dl, al
13c9           adc ecx, ecx
1bd6           sbb edx, esi
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@bwrsandman
bwrsandman committed Dec 26, 2024
1 parent 59242dc commit bfaf1ae
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Showing 2 changed files with 60 additions and 24 deletions.
48 changes: 24 additions & 24 deletions llvm/lib/Target/X86/X86InstrArithmetic.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -626,10 +626,10 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
let isCommutable = CommutableRR,
isConvertibleToThreeAddress = ConvertibleToThreeAddressRR in {
let Predicates = [NoNDD] in {
def 8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
def 16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>, OpSize16;
def 32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>, OpSize32;
def 64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
def 8rr : BW1_BinOpRR_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>;
def 16rr : BW1_BinOpRR_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>, OpSize16;
def 32rr : BW1_BinOpRR_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>, OpSize32;
def 64rr : BW1_BinOpRR_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>;
}
let Predicates = [HasNDD, In64BitMode] in {
def 8rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag, 1>;
Expand All @@ -653,10 +653,10 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
}
}

def 8rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi8>;
def 16rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi64>;
def 8rr_REV : BW1_BinOpRR_RF_Rev<BaseOpc, mnemonic, Xi8>;
def 16rr_REV : BW1_BinOpRR_RF_Rev<BaseOpc, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BW1_BinOpRR_RF_Rev<BaseOpc, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BW1_BinOpRR_RF_Rev<BaseOpc, mnemonic, Xi64>;
let Predicates = [In64BitMode] in {
def 8rr_EVEX_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi8>, PL;
def 16rr_EVEX_REV : BinOpRR_RF_Rev<BaseOpc2, mnemonic, Xi16>, PL, PD;
Expand Down Expand Up @@ -844,11 +844,11 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
bit ConvertibleToThreeAddress> {
let isCommutable = CommutableRR in {
let Predicates = [NoNDD] in {
def 8rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi8 , opnode>;
def 8rr : BW1_BinOpRRF_RF<BaseOpc2, mnemonic, Xi8 , opnode>;
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
def 16rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi16, opnode>, OpSize16;
def 32rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
def 64rr : BinOpRRF_RF<BaseOpc, mnemonic, Xi64, opnode>;
def 16rr : BW1_BinOpRRF_RF<BaseOpc2, mnemonic, Xi16, opnode>, OpSize16;
def 32rr : BW1_BinOpRRF_RF<BaseOpc2, mnemonic, Xi32, opnode>, OpSize32;
def 64rr : BW1_BinOpRRF_RF<BaseOpc2, mnemonic, Xi64, opnode>;
}
}
let Predicates = [HasNDD, In64BitMode] in {
Expand All @@ -868,10 +868,10 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
def 64rr_EVEX : BinOpRRF_RF<BaseOpc, mnemonic, Xi64, null_frag>, PL;
}

def 8rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi8>;
def 16rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi64>;
def 8rr_REV : BW1_BinOpRRF_RF_Rev<BaseOpc, mnemonic, Xi8>;
def 16rr_REV : BW1_BinOpRRF_RF_Rev<BaseOpc, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BW1_BinOpRRF_RF_Rev<BaseOpc, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BW1_BinOpRRF_RF_Rev<BaseOpc, mnemonic, Xi64>;
let Predicates = [In64BitMode] in {
def 8rr_ND_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi8, 1>;
def 16rr_ND_REV : BinOpRRF_RF_Rev<BaseOpc2, mnemonic, Xi16, 1>, PD;
Expand Down Expand Up @@ -1009,18 +1009,18 @@ multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
SDNode opnode, bit CommutableRR,
bit ConvertibleToThreeAddress> {
let isCommutable = CommutableRR in {
def 8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>;
def 8rr : BW1_BinOpRR_F<BaseOpc2, mnemonic, Xi8 , opnode>;
let isConvertibleToThreeAddress = ConvertibleToThreeAddress in {
def 16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>, OpSize16;
def 32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
def 64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;
def 16rr : BW1_BinOpRR_F<BaseOpc2, mnemonic, Xi16, opnode>, OpSize16;
def 32rr : BW1_BinOpRR_F<BaseOpc2, mnemonic, Xi32, opnode>, OpSize32;
def 64rr : BW1_BinOpRR_F<BaseOpc2, mnemonic, Xi64, opnode>;
} // isConvertibleToThreeAddress
} // isCommutable

def 8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>;
def 16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>;
def 8rr_REV : BW1_BinOpRR_F_Rev<BaseOpc, mnemonic, Xi8>;
def 16rr_REV : BW1_BinOpRR_F_Rev<BaseOpc, mnemonic, Xi16>, OpSize16;
def 32rr_REV : BW1_BinOpRR_F_Rev<BaseOpc, mnemonic, Xi32>, OpSize32;
def 64rr_REV : BW1_BinOpRR_F_Rev<BaseOpc, mnemonic, Xi64>;

def 8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>;
def 16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>, OpSize16;
Expand Down
36 changes: 36 additions & 0 deletions llvm/lib/Target/X86/X86InstrUtils.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -984,6 +984,16 @@ class BinOpRR_F_Rev<bits<8> o, string m, X86TypeInfo t>
: BinOpRR_F<o, m, t, null_frag>, DisassembleOnly {
let Form = MRMSrcReg;
}
class BW1_BinOpRR_F<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node>
: BinOpRR<o, m, binop_args, t, (outs),
[(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
DefEFLAGS {
let Form = MRMSrcReg;
}
class BW1_BinOpRR_F_Rev<bits<8> o, string m, X86TypeInfo t>
: BinOpRR_F<o, m, t, null_frag>, DisassembleOnly {
let Form = MRMDestReg;
}
// BinOpRR_R - Instructions that read "reg, reg" and write "reg".
class BinOpRR_R<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,
Expand All @@ -1004,6 +1014,19 @@ class BinOpRR_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
: BinOpRR_RF<o, m, t, null_frag, ndd>, DisassembleOnly {
let Form = MRMSrcReg;
}

class BW1_BinOpRR_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t,
(outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS,
(node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd> {
let Form = MRMSrcReg;
}
class BW1_BinOpRR_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
: BinOpRR_RF<o, m, t, null_frag, ndd>, DisassembleOnly {
let Form = MRMDestReg;
}

// BinOpRRF_RF - Instructions that read "reg, reg", write "reg" and read/write
// EFLAGS.
class BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
Expand All @@ -1019,6 +1042,19 @@ class BinOpRRF_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
let Form = MRMSrcReg;
}

class BW1_BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS,
(node t.RegClass:$src1, t.RegClass:$src2,
EFLAGS))]>, DefEFLAGS, UseEFLAGS, NDD<ndd> {
let SchedRW = [WriteADC];
let Form = MRMSrcReg;
}
class BW1_BinOpRRF_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
: BinOpRRF_RF<o, m, t, null_frag, ndd>, DisassembleOnly {
let Form = MRMDestReg;
}

// BinOpRM - Instructions that read "reg, [mem]".
class BinOpRM<bits<8> o, string m, string args, X86TypeInfo t, dag out, list<dag> p>
: ITy<o, MRMSrcMem, t, out, (ins t.RegClass:$src1, t.MemOperand:$src2), m,
Expand Down

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