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SERV 1.2.0
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@olofk olofk released this 25 Jul 23:50
· 95 commits to main since this release
1.2.0
cb4276e

New features

The 1.2.0 version of the award-winning SERV, the world's smallest RISC-V CPU focuses on features rather than size reduction as has previously been the case. Most notably, two major ISA extensions are now supported but there are also a number of other new features as can be seen below.

Servant

The SERV reference SoC, Servant, has gained support for the following new FPGA boards:

  • EBAZ4205
  • Chameleion96
  • Nexys2 500
  • Nexys2 1200
  • Alinx AX309

With this, the total number of officially supported boards is 26

M extension

As part of Google Summer of Code 2021, Zeeshan Rafique implemented support for the M ISA extension. This was done through an extension interface that allows the MDU (multiplication and division unit) to reside outside of the core and potentially be shared by several SERV cores in the same SoC or integrated into other RISC-V cores for maximum reusability. Zeeshan's report about the project to add the M extension can be read here

C extension

As part of the Linux Foundation Mentorship program Spring 2022, Abdul Wadood has implemented support for the C ISA extension. The C extension has been the most requested feature of SERV. Since SERV is so small, the memory typically dominates the area and the C extension has the potential to allow for smaller memories and by extension a smaller system. Abdul's report about the project to add the C extension can be read here

ViDBo support

Support for the Virtual Development Board protocol has been added, making it possible to interact with a simulation of an FPGA board running a SERV SoC, just as it would be a real board. This allows anyone to build software for SERV and try it in simulation without access to a real board.

OpenLANE support

Thanks to the FOSSi OpenLANE toolchain, SERV can be implemented as an ASIC with the SkyWater 130nm library. It has also been fabbed as part of the Subservient SoC but at the time of this release the chips have not yet returned from the fab. Thanks to the combination of a FuseSoC, a FOSSi ASIC toolchain and publicly available CI resources however, a GDS file of SERV is now created on every commit to the repository, making the ASIC process about as agile as it can get.

Documentation

Documentation continue to improve with more gate-level schematics, written documentation, source code comments and timing diagrams towards the goal of becoming the best documented RISC-V CPU.

Bug fixes

  • A bug that caused immediates to occasionally get the wrong sign (depending on which instruction was executed prior to the failing one) was found and fixed.
  • Model/QuestaSim compatibility has been restored after accidentally being broken after the 1.1.0 release.

Compliance tests

Version 2.7.4 of the RISC-V compliance test suite is now supported over the older 1.0 release. A Github CI action has also been created to test the compliance test suites with all valid combinations of ISA extensions for improved test coverage.

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