samples: benchmarks: coremark: add FLPR support for nRF54L15 DK

Added the FLPR core support for the nRF54L15 DK board target in the
CoreMark sample.

Ref: NCSDK-30327

Signed-off-by: Kamil Piszczek <[email protected]>

doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst

@@ -574,7 +574,10 @@ Other samples
 
 * :ref:`coremark_sample` sample:
 
-  * Added support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
+  * Added:
+
+    * Support for the nRF54L05 and nRF54L10 SoCs (emulated on nRF54L15 DK).
+    * FLPR core support for the :ref:`zephyr:nrf54l15dk_nrf54l15` board target.
 
 Drivers
 =======

samples/benchmarks/coremark/Kconfig

@@ -6,10 +6,13 @@
 
 menu "CoreMark sample"
 
+config APP_BUTTON_AND_LED_SUPPORTED
+	bool
+	default y if $(dt_alias_enabled,button) && $(dt_alias_enabled,led)
+
 config APP_MODE_FLASH_AND_RUN
-	bool "Run CoreMark benchmark on start up" if \
-		!(SOC_NRF54H20_CPUPPR)
-	default y if SOC_NRF54H20_CPUPPR
+	bool "Run CoreMark benchmark on start up" if APP_BUTTON_AND_LED_SUPPORTED
+	default y if !APP_BUTTON_AND_LED_SUPPORTED
 	help
 	  If enabled, CoreMark will start execution immediately after the CPU starts up.
 	  It also disables LEDs and buttons.

samples/benchmarks/coremark/Kconfig.sysbuild

@@ -6,6 +6,11 @@
 
 source "share/sysbuild/Kconfig"
 
+config APP_CPUFLPR_RUN
+	bool "Run the CoreMark benchmark on the FLPR core"
+	depends on SUPPORT_FLPRCORE && !SOC_NRF54H20_CPUAPP
+	default y
+
 config APP_CPUNET_RUN
 	bool "Run the CoreMark benchmark on the network or radio core"
 	depends on SUPPORT_NETCORE

samples/benchmarks/coremark/README.rst

@@ -77,33 +77,29 @@ Each target CPU has an assigned button responsible for starting the benchmark an
 
 .. tabs::
 
-   .. group-tab:: nRF52 and nRF53 DKs
+   .. group-tab:: nRF52 DKs
 
-      Button 1:
-         Start the benchmark run on the application core.
+      Application core: **Button 1** and **LED 1**
 
-      Button 2:
-         Start the benchmark run on the network or radio core.
+   .. group-tab:: nRF53 DKs
 
-      LED 1:
-         Indicates ``test in progress`` on the application core.
+      Application core: **Button 1** and **LED 1**
 
-      LED 2:
-         Indicates ``test in progress`` on the network or radio core.
+      Network core: **Button 2** and **LED 2**.
 
-   .. group-tab:: nRF54 DKs
+   .. group-tab:: nRF54L DKs
 
-      Button 0:
-         Start the benchmark run on the application core.
+      Application core: **Button 0** and **LED 0**
 
-      Button 1:
-         Start the benchmark run on the network or radio core.
+      FLPR core: **Button 3** and **LED 3**
 
-      LED 0:
-         Indicates ``test in progress`` on the application core.
+        This UI is currently only supported for the ``nrf54l15dk/nrf54l15/cpuapp`` board target.
 
-      LED 1:
-         Indicates ``test in progress`` on the network or radio core.
+   .. group-tab:: nRF54H DKs
+
+      Application core: **Button 0** and **LED 0**
+
+      Radio core: **Button 1** and **LED 1**
 
 .. _coremark_configuration:
 
@@ -171,18 +167,33 @@ CONFIG_APP_MODE_FLASH_AND_RUN - Start CoreMark sample automatically after flashi
    Otherwise, it will wait for the button press.
 
 .. note::
-   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core.
-   This core does not use buttons.
+   The :kconfig:option:`CONFIG_APP_MODE_FLASH_AND_RUN` Kconfig option is always enabled for the PPR core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target.
+   This core on the ``nrf54h20dk/nrf54h20/cpuapp`` board target does not use the on-board buttons and LEDs.
+
+.. _SB_CONFIG_APP_CPUFLPR_RUN:
+
+SB_CONFIG_APP_CPUFLPR_RUN - Enable the benchmark execution also for the FLPR core
+   This option is only available for board targets that support the FLPR core (for example, ``nrf54l15dk/nrf54l15/cpuapp``) in this sample.
+
+.. note::
+   FLPR code is run from RAM.
+
+   This option is not supported for the following board targets that include an SoC with the FLPR core:
+
+     * ``nrf54h20dk/nrf54h20/cpuapp``
+     * ``nrf54l15dk/nrf54l05/cpuapp``
+     * ``nrf54l15dk/nrf54l10/cpuapp``
 
 .. _SB_CONFIG_APP_CPUNET_RUN:
 
-SB_CONFIG_APP_CPUNET_RUN - Enable execution for the network core or the radio core
-   Enable the benchmark execution for the network core for targets with the nRF53 Series SoCs, and for the radio core on targets with the nRF54H20 SoCs.
+SB_CONFIG_APP_CPUNET_RUN - Enable the benchmark execution also for the network core or the radio core
+   This option is only available for board targets that support the network core (for example, ``nrf5340dk/nrf5340/cpuapp``) or radio core (for example, ``nrf54h20dk/nrf54h20/cpuapp``) in this sample .
 
 .. _SB_CONFIG_APP_CPUPPR_RUN:
 
-SB_CONFIG_APP_CPUPPR_RUN - Enable execution for the PPR core
-   Enable the benchmark execution also for the PPR core for targets with the nRF54H20 SoCs.
+SB_CONFIG_APP_CPUPPR_RUN - Enable the benchmark execution also for the PPR core
+   This option is only available for board targets that support the PPR core (for example, ``nrf54h20dk/nrf54h20/cpuapp``) in this sample.
+
 
 .. note::
    PPR code is run from RAM.

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+ #include "app_aliases_common.overlay"
+
+/* The following configuration is required to run the CPUFLPR core.
+ * It is imported from the nordic-flpr snippet.
+ */
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpuflpr_code_partition: image@165000 {
+				/* FLPR core code partition */
+				reg = <0x165000 DT_SIZE_K(96)>;
+			};
+		};
+
+		cpuflpr_sram_code_data: memory@20028000 {
+			compatible = "mmio-sram";
+			reg = <0x20028000 DT_SIZE_K(96)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20028000 0x18000>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(160)>;
+	ranges = <0x0 0x20000000 0x28000>;
+};
+
+&cpuflpr_vpr {
+	status = "okay";
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
+
+/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
+ * This is done to allow control over one Button and one LED in each core. The benchmark code is
+ * responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
+ * instance that may be used with the GPIO pin (Button).
+ */

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_COREMARK_ITERATIONS=4000
+
+CONFIG_LOG_MODE_IMMEDIATE=y

samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	aliases {
+		button = &button3;
+		led = &led3;
+	};
+};
+
+/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
+ * This is done to allow control over one Button and one LED in each core. The benchmark code is
+ * responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
+ * instance that may be used with the GPIO pin (Button).
+ */

samples/benchmarks/coremark/sysbuild.cmake

@@ -5,6 +5,15 @@
 
 include_guard(GLOBAL)
 
+if(SB_CONFIG_APP_CPUFLPR_RUN)
+  ExternalZephyrProject_Add(
+    APPLICATION coremark_${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
+    SOURCE_DIR ${APP_DIR}
+    BOARD ${SB_CONFIG_BOARD}/${SB_CONFIG_SOC}/${SB_CONFIG_FLPRCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}
+    BOARD_REVISION ${BOARD_REVISION}
+  )
+endif()
+
 if(SB_CONFIG_APP_CPUNET_RUN)
   ExternalZephyrProject_Add(
     APPLICATION coremark_${SB_CONFIG_NETCORE_REMOTE_BOARD_TARGET_CPUCLUSTER}