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A RISCV emulator built in Rust

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duna

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An assembly simulator built in Rust.

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Current functionality

  • Run by CLI with cargo run <INPUT_FILE>
  • RISC-V
    • Supports most of RV32IM and RV64IM
    • Supports a few ecalls
  • MIPS
    • WIP

Roadmap

RISC-V

  • Finish multiplication extension
  • Figure out which CSRs to support

OS/Memory

  • Fix page table/TLB lol
  • Instruction decoding + instruction fetches
  • Distinguish between IMEM/DMEM
  • Interrupts?
  • Kernel memory?
  • Fence instructions
  • Configurable cache hierarchy, store buffers

Interface

  • Standard library functions
  • CLI configuration
  • Support assembler relocation functions
  • Display regfile, memory, and cache info
  • Ability to poke values in registers, memory, etc. (add sources/causes to diff structs?)
  • Provide debugger support a la GDB, possibly valgrind-like tools as well?
  • Implement peephole optimizations + visualizations

Niceties

Other ISAs?

  • MIPS 32/64bit? whatever they're called?
  • Atmel AVR
  • ARM
  • x86-64
  • wasm
  • some LLVM IR

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A RISCV emulator built in Rust

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