Merge remote-tracking branch 'fsl-linux-sdk/imx_5.4.47_2.2.0' into im…

…x_5.4.47_2.2.0_android-r Conflicts: arch/arm64/boot/dts/freescale/imx8mn-evk.dts arch/arm64/boot/dts/freescale/imx8mq-evk.dts Change-Id: Iada7e9215d81509e8291916467675414fce43950 Signed-off-by: Jindong <[email protected]>
nikhilanjane03 · Sep 24, 2020 · f997ffd · f997ffd
2 parents b27a8ba + 5ec03d0
commit f997ffd
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Showing 106 changed files with 2,399 additions and 704 deletions.
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt
@@ -9,7 +9,8 @@ Required properties:
 
 Optional properties:
 - vbus-supply: A phandle to the regulator for USB VBUS.
-
+- vbus-power-supply: A phandle to the vbus power supply provider, used to
+		     to detect the possible BC charger type of it.
 Example:
 	usb3_phy0: phy@381f0040 {
 		compatible = "fsl,imx8mq-usb-phy";

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
@@ -724,6 +724,8 @@
 				clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
 					<&clks IMX7D_ECSPI4_ROOT_CLK>;
 				clock-names = "ipg", "per";
+				dmas = <&sdma 6 7 1>, <&sdma 7 7 2>;
+				dma-names = "rx", "tx";
 				status = "disabled";
 			};
 
@@ -857,6 +859,8 @@
 					clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
 						<&clks IMX7D_ECSPI1_ROOT_CLK>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 0 7 1>, <&sdma 1 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -869,6 +873,8 @@
 					clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
 						<&clks IMX7D_ECSPI2_ROOT_CLK>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 2 7 1>, <&sdma 3 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 
@@ -881,6 +887,8 @@
 					clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
 						<&clks IMX7D_ECSPI3_ROOT_CLK>;
 					clock-names = "ipg", "per";
+					dmas = <&sdma 4 7 1>, <&sdma 5 7 2>;
+					dma-names = "rx", "tx";
 					status = "disabled";
 				};
 

diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -292,6 +292,7 @@
 &lpi2c5 {
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clock-frequency = <100000>;
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_lpi2c5>;
 	pinctrl-1 = <&pinctrl_lpi2c5>;
@@ -370,6 +371,7 @@
 &lpi2c7 {
 	#address-cells = <1>;
 	#size-cells = <0>;
+	clock-frequency = <100000>;
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_lpi2c7 &pinctrl_touch_io>;
 	pinctrl-1 = <&pinctrl_lpi2c7 &pinctrl_touch_io>;

diff --git a/arch/arm/configs/imx_v7_defconfig b/arch/arm/configs/imx_v7_defconfig
@@ -151,6 +151,10 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_IMX=y
 CONFIG_PATA_IMX=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
 CONFIG_NETDEVICES=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
 CONFIG_CS89x0=y

diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -55,6 +55,9 @@ static void __init imx7ulp_set_revision(void)
 	case 2:
 		imx_set_soc_revision(IMX_CHIP_REVISION_2_1);
 		break;
+	case 3:
+		imx_set_soc_revision(IMX_CHIP_REVISION_2_2);
+		break;
 	default:
 		imx_set_soc_revision(IMX_CHIP_REVISION_1_0);
 		break;

diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -117,6 +117,13 @@
 
 #define ADDR_1M_MASK	0xFFF00000
 
+#define WDOG_CS			0x0
+#define WDOG_CS_CMD32EN		BIT(13)
+#define WDOG_CNT	0x4
+#define REFRESH_SEQ0	0xA602
+#define REFRESH_SEQ1	0xB480
+#define REFRESH		((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
+
 static void __iomem *smc1_base;
 static void __iomem *pmc0_base;
 static void __iomem *pmc1_base;
@@ -127,6 +134,7 @@ static void __iomem *pcc2_base;
 static void __iomem *pcc3_base;
 static void __iomem *mu_base;
 static void __iomem *scg1_base;
+static void __iomem *wdog1_base;
 static void __iomem *gpio_base[4];
 static void __iomem *suspend_ocram_base;
 static void (*imx7ulp_suspend_in_ocram_fn)(void __iomem *sram_base);
@@ -462,6 +470,20 @@ static int imx7ulp_suspend_finish(unsigned long val)
 	return 0;
 }
 
+static void imx7ulp_wdog_refresh(void)
+{
+	/*
+	 * On revision 2.2, wdog2 is by default disabled when out of
+	 * reset, so here, we ONLY refresh wdog1.
+	 */
+	if (readl_relaxed(wdog1_base + WDOG_CS) & WDOG_CS_CMD32EN) {
+		writel(REFRESH, wdog1_base + WDOG_CNT);
+	} else {
+		writel_relaxed(REFRESH_SEQ0, wdog1_base + WDOG_CNT);
+		writel_relaxed(REFRESH_SEQ1, wdog1_base + WDOG_CNT);
+	}
+}
+
 static int imx7ulp_pm_enter(suspend_state_t state)
 {
 	switch (state) {
@@ -515,6 +537,8 @@ static int imx7ulp_pm_enter(suspend_state_t state)
 		return -EINVAL;
 	}
 
+	imx7ulp_wdog_refresh();
+
 	return 0;
 }
 
@@ -704,6 +728,10 @@ void __init imx7ulp_pm_common_init(const struct imx7ulp_pm_socdata
 	scg1_base = of_iomap(np, 0);
 	WARN_ON(!scg1_base);
 
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-wdt");
+	wdog1_base = of_iomap(np, 0);
+	WARN_ON(!wdog1_base);
+
 	np = NULL;
 	for (i = 0; i < 4; i++) {
 		np = of_find_compatible_node(np, NULL, "fsl,vf610-gpio");

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
@@ -867,6 +867,11 @@ static int __init __l2c_init(const struct l2c_init_data *data,
 		l2x0_saved_regs.aux_ctrl = aux;
 
 		data->enable(l2x0_base, data->num_lock);
+	} else {
+		pr_info("%s cache controller enabled try to unlock\n",
+			data->type);
+
+		data->unlock(l2x0_base, data->num_lock);
 	}
 
 	outer_cache = fns;

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
@@ -58,7 +58,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk
 			  imx8mm-ddr4-evk-no-dynamic_partition.dtb imx8mm-ddr4-evk-no-product-no-dynamic_partition.dtb \
 			  imx8mm-evk-no-dynamic_partition.dtb imx8mm-evk-no-product-no-dynamic_partition.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb
-dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb imx8mm-ab2-m4.dtb imx8mm-ddr4-ab2.dtb imx8mm-ddr4-ab2-m4.dtb \
+			  imx8mm-ddr4-ab2-revb.dtb imx8mm-ddr4-ab2-m4-revb.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \
 			  imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \
 			  imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb imx8mn-evk-8mic-revE.dtb \

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts b/arch/arm64/boot/dts/freescale/imx8dxl-ddr3-val.dts
@@ -8,7 +8,7 @@
 #include "imx8dxl.dtsi"
 
 / {
-	model = "Freescale i.MX8DXL DDR3 EVK";
+	model = "Freescale i.MX8DXL DDR3 VAL";
 	compatible = "fsl,imx8dxl-mek", "fsl,imx8dxl";
 
 	chosen {

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk-pcie-ep.dts
@@ -5,7 +5,7 @@
 
 /dts-v1/;
 
-#include "imx8dxl-evk.dts"
+#include "imx8dxl-evk-rpmsg.dts"
 
 &pcieb {
 	status = "disabled";

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -186,6 +186,7 @@
 		regulator-max-microvolt = <3300000>;
 		regulator-name = "clk_ext_sel";
 		gpio = <&pca6416_1 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
 		regulator-always-on;
 	};
 
@@ -892,7 +893,7 @@
 			fsl,pins = <
 				IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC     0x06000040
 				IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS    0x06000040
-				IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD     0x06000040
+				IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD     0x06000060
 				IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD     0x06000060
 			>;
 		};

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2-m4.dts
@@ -14,7 +14,7 @@
 		ranges;
 
 		m4_reserved: m4@0x80000000 {
-			reg = <0 0x80000000 0 0x1000000>;
+			reg = <0 0x80000000 0 0x0101E400>;
 			no-map;
 		};
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mm-ab2.dts
@@ -585,6 +585,13 @@
 	};
 };
 
+&i2c4 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c4>;
+	status = "disabled";
+};
+
 &iomuxc {
 	pinctrl-names = "default";
 
@@ -647,6 +654,13 @@
 		>;
 	};
 
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL			0x400001c3
+			MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA			0x400001c3
+		>;
+	};
+
 	pinctrl_mipi_dsi_en: mipi_dsi_en {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x16
@@ -697,6 +711,12 @@
 			MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
 			MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
 			MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0	0xd6
+			MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1	0xd6
+			MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2	0xd6
+			MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3	0xd6
+			MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC	0xd6
+			MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK	0xd6
 		>;
 	};
 
@@ -713,6 +733,12 @@
 			MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5	0xd6
 			MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6	0xd6
 			MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7	0xd6
+			MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0	0xd6
+			MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1	0xd6
+			MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2	0xd6
+			MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3	0xd6
+			MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC	0xd6
+			MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK	0xd6
 		>;
 	};
 

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4-revb.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm-ddr4-ab2-m4.dts"
+
+/ {
+	model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0";
+};
+
+/*
+ * External OSC is used as PCIe REFCLK on RevC board.
+ * Use the -revb.dts file to distiguish the different
+ * HW design.
+ */
+&pcie0 {
+	ext_osc = <0>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-m4.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm-ddr4-ab2.dts"
+
+/ {
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		m4_reserved: m4@0x80000000 {
+			reg = <0 0x80000000 0 0x0101E400>;
+			no-map;
+		};
+
+		vdev0vring0: vdev0vring0@b8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xb8000000 0 0x8000>;
+			no-map;
+		};
+
+		vdev0vring1: vdev0vring1@b8008000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xb8008000 0 0x8000>;
+			no-map;
+		};
+
+		vdevbuffer: vdevbuffer@b8400000 {
+			compatible = "shared-dma-pool";
+			reg = <0 0xb8400000 0 0x100000>;
+			no-map;
+		};
+	};
+
+	leds {
+		panel {
+			status = "disabled";
+		};
+	};
+
+	imx8mm-cm4 {
+		compatible = "fsl,imx8mm-cm4";
+		rsc-da = <0xb8000000>;
+		clocks = <&clk IMX8MM_CLK_M4_DIV>;
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&mu 0 1
+			  &mu 1 1
+			  &mu 3 1>;
+		memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>;
+		syscon = <&src>;
+	};
+};
+
+&clk {
+	init-on-array = <
+		IMX8MM_CLK_UART4_ROOT
+		IMX8MM_CLK_AHB IMX8MM_CLK_DRAM_CORE
+		IMX8MM_CLK_NOC IMX8MM_CLK_NOC_APB
+		IMX8MM_CLK_MAIN_AXI IMX8MM_CLK_AUDIO_AHB
+		IMX8MM_CLK_DRAM_APB IMX8MM_CLK_A53_DIV
+		IMX8MM_ARM_PLL_OUT
+	>;
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&uart4 {
+	status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-ab2-revb.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm-ddr4-ab2.dts"
+
+/ {
+	model = "FSL i.MX8MM DDR4 RevB Audio Board 2.0";
+};
+
+/*
+ * External OSC is used as PCIe REFCLK on RevC board.
+ * Use the -revb.dts file to distiguish the different
+ * HW design.
+ */
+&pcie0 {
+	ext_osc = <0>;
+	status = "okay";
+};
-Original file line number
+Diff line change
@@ Expand Up / @@ -14,7 +14,7 @@ @@
     		ranges;
     		m4_reserved: m4@0x80000000 {
-    			reg = <0 0x80000000 0 0x1000000>;
+    			reg = <0 0x80000000 0 0x0101E400>;
     			no-map;
     		};
@@ Expand Down @@