Add hw timed examples for exisiting sw timed examples #561

WayneDroid · 2024-04-09T02:52:27Z

This contribution adheres to CONTRIBUTING.md.

What does this Pull Request accomplish?

Added HW timed examples for existing SW timed examples.

Why should this Pull Request be merged?

Currently, we only have SW timed examples except ao_voltage_hw_timed.py, this PR is to add HW timed examples for the rest of SW timed examples.

What testing has been done?

poetry run pytest tests/ -q - pass

zhindes · 2024-04-09T19:47:54Z

examples/ai_voltage_hw_timed.py

@@ -0,0 +1,43 @@
+"""Example of AI voltage sw operation."""


Suggested change

"""Example of AI voltage sw operation."""

"""Example of AI voltage hardware-timed finite acquisition."""

English has a standard order for using multiple adjectives: https://www.grammarly.com/blog/adjective-order/ . If you don't follow this order, it sounds slightly awkward.

The existing examples don't follow this order and have other style problems like lowercase "sw".

It would be better to reword the text so that it doesn't contain a long list of adjectives. Consider reusing text from the LabVIEW, ANSI C, CVI, or .NET examples. For example:

This example demonstrates how to acquire a finite amount of data using the DAQ device's internal clock.

The description is updated by referring LabVIEW examples.

zhindes · 2024-04-09T19:48:45Z

examples/ai_voltage_hw_timed.py

+
+with nidaqmx.Task() as task:
+    task.ai_channels.add_ai_voltage_chan("cDAQ1Mod1/ai0")
+    task.timing.cfg_samp_clk_timing(1000)


Specify these two optional params

Suggested change

task.timing.cfg_samp_clk_timing(1000)

task.timing.cfg_samp_clk_timing(1000, sample_mode=AcquisitionType.FINITE, samps_per_chan=1000)

noted, optional params are added for the files which called cfg_samp_clk_timing.

zhindes · 2024-04-09T19:51:58Z

examples/ai_voltage_hw_timed.py

+    print("1 Channel 1 Sample Read: ")
+    data = task.read()
+    pp.pprint(data)
+    task.wait_until_done()
+    task.stop()
+
+    data = task.read(number_of_samples_per_channel=1)
+    pp.pprint(data)
+    task.wait_until_done()
+    task.stop()
+
+    print("1 Channel N Samples Read: ")
+    data = task.read(number_of_samples_per_channel=8)
+    pp.pprint(data)
+    task.wait_until_done()
+    task.stop()
+
+    task.ai_channels.add_ai_voltage_chan("cDAQ1Mod1/ai1:3")
+
+    print("N Channel 1 Sample Read: ")
+    data = task.read()
+    pp.pprint(data)
+    task.wait_until_done()
+    task.stop()
+
+    print("N Channel N Samples Read: ")
+    data = task.read(number_of_samples_per_channel=2)
+    print(data)
+    task.wait_until_done()
+    task.stop()


Let's simplify

Suggested change

print("1 Channel 1 Sample Read: ")

data = task.read()

pp.pprint(data)

task.wait_until_done()

task.stop()

data = task.read(number_of_samples_per_channel=1)

pp.pprint(data)

task.wait_until_done()

task.stop()

print("1 Channel N Samples Read: ")

data = task.read(number_of_samples_per_channel=8)

pp.pprint(data)

task.wait_until_done()

task.stop()

task.ai_channels.add_ai_voltage_chan("cDAQ1Mod1/ai1:3")

print("N Channel 1 Sample Read: ")

data = task.read()

pp.pprint(data)

task.wait_until_done()

task.stop()

print("N Channel N Samples Read: ")

data = task.read(number_of_samples_per_channel=2)

print(data)

task.wait_until_done()

task.stop()

print("Reading Data: ")

task.start()

data = task.read()

print(data)

task.stop()

Done, it's updated.

zhindes · 2024-04-09T19:55:08Z

examples/ai_voltage_hw_timed.py

@@ -0,0 +1,43 @@
+"""Example of AI voltage sw operation."""


Rename this file ai_voltage_hw_timed_finite.py and let's create one more that is a duplicate, but called ai_voltage_hw_timed_continues.py. The main difference will be:

change the params to cfg_samp_clk_timing

pass in number_of_samples_per_channel to task.read (1/10th of your sample rate)

loop forever reading between start/stop

try/catch waiting for a keyboard interrupt to stop (user presses Ctrl+C, ask them to do that in a print)

@zhindes Have you considered copying the naming of the LabVIEW, ANSI C, CVI, or .NET examples, e.g. ai_acq_int_clk.py, ai_cont_acq_int_clk.py?

or even analog_in/acq_int_clk.py etc.

Yeah, I like that!

@zhindes I'm not sure should we add continuous example as the examples will be run together with the pytest under acceptance folder, I think that will break the pytest.

Oh, that's a fair point. We'll need some way to not run tests that are continuous. We should still have the examples, though.

Oh yeah, just find that we already have continuous examples taken care, the test will skip if KeyboardInterrupt is found in the example.

Created sub folders for AI, AO, DI, DO, CI and CO examples, including continuous examples.

zhindes · 2024-04-09T19:58:38Z

examples/ci_hw_count_edges.py

+    task.ci_channels.add_ci_count_edges_chan("Dev1/ctr0")
+    task.timing.cfg_samp_clk_timing(1000, "/Dev1/PFI6")


sample clocks with event counts aren't common. I think this is what you want:

Suggested change

task.ci_channels.add_ci_count_edges_chan("Dev1/ctr0")

task.timing.cfg_samp_clk_timing(1000, "/Dev1/PFI6")

task.ci_channels.add_ci_count_edges_chan("Dev1/ctr0").ci_count_edges_term = "Dev1/PFI6"

probably cleaner on two lines. save the channel to a variable then set the ci_count_edges_term

ci_hw_count_edges.py is renamed to ci_count_edges_ext_clk.py. I still keep the cfg_samp_clk_timing in example to align with LabVIEW example Counter - Count Edges (Finite Clock).vi.

zhindes · 2024-04-09T20:02:44Z

examples/di_hw_timed.py

+with nidaqmx.Task() as task:
+    task.di_channels.add_di_chan("Dev1/port0/line0:3", line_grouping=LineGrouping.CHAN_PER_LINE)
+    task.timing.cfg_samp_clk_timing(1000)
+
+    print("N Channel 1 Sample Read: ")
+    data = task.read()
+    pp.pprint(data)
+    task.wait_until_done()
+    task.stop()
+
+    print("N Channel N Samples Read: ")
+    data = task.read(number_of_samples_per_channel=3)
+    print(data)
+    task.wait_until_done()
+    task.stop()


follow AI review comments

two examples - finite, continuous

etcetc

Okay, all examples are updated according to your suggestions.

zhindes · 2024-04-09T20:03:00Z

examples/do_hw_timed.py

+    print("1 Channel N Lines 1 Sample Unsigned Integer Write: ")
+    print(task.write(8))


It's deleted.

zhindes · 2024-04-09T20:03:25Z

examples/do_hw_timed.py

+    task.do_channels.add_do_chan(
+        "Dev1/port0/line0:3", line_grouping=LineGrouping.CHAN_FOR_ALL_LINES
+    )
+    task.timing.cfg_samp_clk_timing(1000)


specify optional params

Optional params are added.

zhindes · 2024-04-09T20:03:37Z

examples/do_hw_timed.py

+    print(task.write(8))
+
+    print("1 Channel N Lines N Samples Unsigned Integer Write: ")
+    print(task.write([1, 2, 4, 8], auto_start=True))


for finite, wait for done then stop task

Okay, it's updated according to your suggestion.

zhindes · 2024-04-09T20:03:42Z

examples/do_hw_timed.py

@@ -0,0 +1,16 @@
+"""Example for writing digital signal."""


add continuous, too

Continuous example is added.

bkeryan · 2024-04-11T17:30:34Z

examples/ai_voltage_hw_timed.py

@@ -0,0 +1,43 @@
+"""Example of AI voltage sw operation."""


English has a standard order for using multiple adjectives: https://www.grammarly.com/blog/adjective-order/ . If you don't follow this order, it sounds slightly awkward.

The existing examples don't follow this order and have other style problems like lowercase "sw".

It would be better to reword the text so that it doesn't contain a long list of adjectives. Consider reusing text from the LabVIEW, ANSI C, CVI, or .NET examples. For example:

This example demonstrates how to acquire a finite amount of data using the DAQ device's internal clock.

bkeryan · 2024-04-11T17:33:14Z

examples/ai_voltage_hw_timed.py

@@ -0,0 +1,43 @@
+"""Example of AI voltage sw operation."""


@zhindes Have you considered copying the naming of the LabVIEW, ANSI C, CVI, or .NET examples, e.g. ai_acq_int_clk.py, ai_cont_acq_int_clk.py?

bkeryan · 2024-04-11T17:38:49Z

examples/ci_hw_count_edges.py

"ci_hw_count_edges.py" makes this sound less advanced / corner-case than it is.

The examples for other ADEs tend to use "buffered" and/or "external clock" to describe this use case.

Cnt-Buf-Cont-ExtClk
Counter - Count Edges (Continuous Clock).vi
etc.

All example files are renamed by referring LabVIEW examples.

bkeryan · 2024-04-17T15:46:12Z

examples/analog_in/ai_voltage_cont_acq.py

@@ -0,0 +1,31 @@
+"""Example of analog input voltage acquisition continuously.


The adverb "continuously" normally modifies a verb, but this is a noun phrase that has no verb.

Suggested change

"""Example of analog input voltage acquisition continuously.

"""Example of continuous analog input voltage acquisition.

bkeryan · 2024-04-17T16:24:01Z

examples/counter_out/co_pulse_time.py

I think you should rename this to dig_pulse.py and copy the logic used in the ANSI C DigPulse.c.

Removing implicit timing changes this from a pulse train to a single pulse.

If it generates a single pulse, "changing pulse specification" no longer has any effect, unless task.write() auto-starts the task, in which case it generates two pulses, which is weird.

time.sleep(2) is the wrong way to wait for a pulse to complete. We should use task.wait_until_done(). (time.sleep(2) was reasonable when this generated a pulse train and we wanted to change the pulse specification while it was running.)

bkeryan · 2024-04-17T16:24:44Z

examples/counter_out/co_pulse_time_cont.py

Rename to dig_pulse_train_cont.py as per ANSI C example DigPulseTrain-Cont.c

bkeryan · 2024-04-17T16:25:33Z

examples/counter_out/co_pulse_time_cont.py

+        sample = CtrTime(high_time=0.001, low_time=0.002)
+        print("Press Ctrl+C to stop")
+        print("1 Channel 1 Sample Write: ")
+        print(task.write(sample, auto_start=True))


Writing during the pulse train is a more advanced use case and we don't have a basic pulse train example. See DigPulseTrain-Cont.c

bkeryan · 2024-04-17T16:26:19Z

examples/counter_out/co_pulse_time_implicit_timing.py

This does a finite pulse train.

Do we need an example of this? We don't have one in C.

bkeryan · 2024-04-17T16:26:39Z

examples/counter_out/co_pulse_time_implicit_timing.py

+    sample = CtrTime(high_time=0.001, low_time=0.002)
+
+    print("1 Channel 1 Sample Write: ")
+    print(task.write(sample))


Again, this is a more advanced use case, and we don't have an example of the basic finite pulse train.

bkeryan · 2024-04-17T16:31:16Z

examples/counter_in/ci_pulse_freq_cont.py

CI pulse channels are an advanced feature that is only supported on devices introduced in 2009 and later. I don't understand why we have examples of these and not the basic stuff:

Measure frequency (with add_ci_freq_chan)

Measure period or pulse width (with add_ci_period_chan)

Measure position (encoders)

Measure 2 edge separation (ok, this is kind of intermediate?)

bkeryan · 2024-04-17T16:32:42Z

examples/digital_in/di_sw_timed.py

read_dig_chan.py?

bkeryan · 2024-04-17T16:35:41Z

examples/ai_voltage_sw_timed.py

At this rate, this PR review is going to take forever.

Here's a proposal for speeding it up:

PR 1: reorganize the existing examples into folders, with no code changes

Let's use Teams to discuss which examples should exist, since many of the existing examples demonstrate advanced features and overlook the basics

PRs 2-7: for each folder, update/rename the examples or replace them with new examples based on the ANSI C examples, when appropriate

ok?

@WayneDroid @zhindes

I agree! I added my first pass thoughts on Teams!

Agree, I created PR for reorganizing example files, #565.
I will close this PR, new changes will be made in another PRs as per suggestion.

Add hw timed examples for exisiting sw timed examples

2e53e62

WayneDroid requested review from zhindes, maxxboehme and bkeryan as code owners April 9, 2024 02:52

fixed dirtied codegen files

87cd3fd

zhindes requested changes Apr 9, 2024

View reviewed changes

bkeryan requested changes Apr 11, 2024

View reviewed changes

added finite and continuous examples

f9668dc

bkeryan requested changes Apr 17, 2024

View reviewed changes

WayneDroid closed this Apr 18, 2024

	"""Example of AI voltage sw operation."""
	"""Example of AI voltage hardware-timed finite acquisition."""

	task.timing.cfg_samp_clk_timing(1000)
	task.timing.cfg_samp_clk_timing(1000, sample_mode=AcquisitionType.FINITE, samps_per_chan=1000)

		task.ci_channels.add_ci_count_edges_chan("Dev1/ctr0")
		task.timing.cfg_samp_clk_timing(1000, "/Dev1/PFI6")

		print("1 Channel N Lines 1 Sample Unsigned Integer Write: ")
		print(task.write(8))

		@@ -0,0 +1,31 @@
		"""Example of analog input voltage acquisition continuously.

	"""Example of analog input voltage acquisition continuously.
	"""Example of continuous analog input voltage acquisition.

Add hw timed examples for exisiting sw timed examples #561

Add hw timed examples for exisiting sw timed examples #561

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WayneDroid commented Apr 9, 2024

What does this Pull Request accomplish?

Why should this Pull Request be merged?

What testing has been done?

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bkeryan Apr 17, 2024 • edited Loading

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bkeryan Apr 17, 2024 •

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