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Homework and Project for Master Course (Synthesis of Digital Systems)

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
HW01		HW01
HW02		HW02
LICENSE		LICENSE
README.md		README.md

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MSc-Synthesis

Homework and Project for Master Course (Synthesis of Digital Systems)

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📝 Homework 01 Solution

📝 Homework 02 Solution

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Homework and Project for Master Course (Synthesis of Digital Systems)

synthesis homework-assignments vhdl-coursework fpga-programming

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VHDL 100.0%