This is it

.dub/dub.json

@@ -0,0 +1,10 @@
+{
+	"dub": {
+		"lastUpgrade": "2018-11-24T13:28:28.1708661",
+		"cachedUpgrades": {
+			"ncurses": "~master",
+			"pdcurses-d": "1.0.0",
+			"dsfml": "~>2.1.1"
+		}
+	}
+}

README.md

@@ -1,5 +1,5 @@
 # 8086eD - x86 Emulator, written in D
-This is self-made x86 interpreter, written in D language. It's private currently, until I polish it more. Expect it very soon
+This is self-made x86 interpreter, written in D language.
 
  ## Supported features:
   * All NEC v20 instructions(unless I missed an instruction(s))

dub.json

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+{
+	"name": "8086ed",
+	"targetname": "8086eD",
+	"authors": [
+		"Geo"
+	],
+	"dependencies": {
+		"dsfml": "~>2.1.1"
+	},
+	"description": "A minimal D application.",
+	"copyright": "Copyright © 2018, Geo",
+	"license": "proprietary"
+}

dub.selections.json

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+{
+	"fileVersion": 1,
+	"versions": {
+		"dsfml": "2.1.1",
+	}
+}

firmware/compile.bat

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+nasm -f bin -o disk_io.bin disk_io.asm
+nasm -f bin -o romimage.bin romimage.asm
+pause

firmware/disk_io.asm

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+USE16
+CPU 186
+
+db 0x55 ; Byte 1
+db 0xAA ; Byte 2
+db 0x10 ; Byte 3
+start:
+cli
+xor ax, ax
+mov ds, ax
+mov word [ds:4Ch], int_13_handler
+mov ax, cs
+mov word [ds:4Eh], ax
+retf
+
+
+int_13_handler:
+db 0xF3
+db 0xF1
+iret
+
+; fill with zeroes till signature
+times    8191-($-$$) db   0x00
+db    0x00   ; checksum

firmware/laststep.bat

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+nasm -f bin -o romimage.bin romimage.asm
+pause

firmware/romimage.asm

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+;VRI image reference file
+;Beginning with HEADER
+
+;Constants
+version equ 0x01
+
+;Actual header
+;First is the unique signature
+db 'VRI', 0
+
+;Next two bytes are bytes for version
+dw version
+
+;Next 256 bytes specify additional information for use in future implementations of the format
+times 256 db 0x00
+
+;Next 4 bytes are the size of the memory descriptor table
+dd memdesctable_end-memdesctable_beg
+
+;Next 4 bytes are the absolute offset to the beginning of the memory descriptor table
+dd memdesctable_beg
+
+;The memory descriptor table
+;Every entry in the table consists of 4x4 bytes:
+;1. 32-bit file offset to the beginning of the memory part
+;2. 32-bit size of the memory part
+;3. 32-bit address in the memory space of the VM
+;4. 32-bit bitfield, specifying various aspects about this memory region
+
+memdesctable_beg:
+
+;Entry 1
+dd main_image_begin
+dd main_image_end-main_image_begin
+dd 0x000FE000 ;Place in the memory space - F000:E000
+dd 0x00000000 ;Bits which specify various properties of the memory space.
+
+;Entry 3
+dd third_image_begin
+dd third_image_end-third_image_begin
+dd 0x000F6000 ;Place in the memory space - F600:0000
+dd 0x00000000 ;Bits which specify various properties of the memory space.
+
+;Entry 4
+dd forth_image_begin
+dd forth_image_end-third_image_begin
+dd 0x000C0000 ;Place in the memory space - F600:0000
+dd 0x00000000 ;Bits which specify various properties of the memory space.
+
+memdesctable_end:
+
+;FFFF:0000
+ORG 0000
+main_image_begin:
+incbin "pcxtbios.bin"
+main_image_end:
+
+;F600:0000
+ORG 0000
+third_image_begin:
+;incbin "program.bin"
+incbin "rombasic.bin"
+third_image_end:
+
+;F600:0000
+ORG 0000
+forth_image_begin:
+;incbin "program.bin"
+incbin "disk_io.bin"
+forth_image_end:
+

pcxtbios31/images/floppy/readme.txt

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+README file for Multi-Floppy BIOS Extension
+*******************************************
+
+General Information
+===================
+
+The Multi-Floppy Floppy BIOS Extension provides support for up to 8 floppy
+drives connected to two floppy disk controllers (FDCs). It supports any
+combination of standard IBM PC/XT/AT and PS/2 floppy drives, with disk sizes
+from 180 KB to 2.88 MB.
+
+Configuration Utility
+---------------------
+
+The BIOS extension has a built-in configuration utility that could be
+invoked by pressing F2 during the boot (BIOS POST). The utility allows setting
+up the floppy drives and FDCs configuration, and saving it to the EEPROM
+(provided that the BIOS extension is in an EEPROM and the write is enabled).
+The ROM is cannot be programmed in system (e.g. write protected, or an EPROM
+chip is used instead of EEPROM), the configuration utility provides a dump
+of the configuration data, so the user can program it manually.
+Please refer to the Implementation Notes section for detailed information on
+the configuration data structure.
+
+Secondary FDC Configuration
+---------------------------
+
+Currently the BIOS extension does not support DMA channel and IRQ sharing with
+the primary FDC. Therefore the secondary FDC must not use DMA channel 2 and
+IRQ 6. 
+
+
+Release Notes
+=============
+
+Version 2.2
+-----------
+- Fix garbage output on CGA displays with IBM BIOS
+- Make BIOS extension code size equal 8 KiB, including the configuration area.
+  This mitigates issues with original IBM BIOS and XT BIOS by Anonymous, that
+  expect BIOS extension size to be a multiply of 2 KiB.
+- Reinstall interrupt vectors on INT 19h.
+
+Version 2.0
+-----------
+
+- Support for two FDCs with up to 8 drives
+- Built-in EEPROM configuration utility
+
+Version 1.0b1
+-------------
+
+- Mostly a straight forward copy of the floppy functions from Xi 8088 BIOS
+
+
+Implementation Notes
+====================
+
+Additional storage for 8 drives support
+---------------------------------------
+
+The Multi-Floppy BIOS extension uses 11 bytes in addition to standard BIOS
+data area variables for storing status information for the secondary FDC and
+drives from 3 to 8.
+
+Here is the list of these variables and their default location:
+
+fdc_media_state_addr:
+- Purpose:		media state for 4 drives on the secondary FDC
+- Size:			4 bytes
+- Default location:	0000:02C0 (interrupt vector 0B0h)
+
+fdc_cylinder_addr:
+- Purpose:		current cylinder for 4 drives on the secondary FDC
+			followed by 2 drives (2 and 3) on the primary FDC
+- Size:			6 bytes
+- Default location:	0000:02C4 (interrupt vectors 0B1h and 0B2h)
+
+fdc_motor_state_addr:
+- Purpose:		mode (read/write), motor state, and selected drive
+			for the secondary FDC
+- Size:			1 byte
+- Default location:	0000:02CA (interrupt vector 0B2h)
+
+In addition the format of the 'last rate' BIOS variable (0040h:008Bh) is
+redifined as follows
+
+bits 7 - 6:	last data rate set for the primary FDC (same as on an AT)
+bits 5 - 4:	not used
+bits 3 - 0:	calibrated bits for the 4 drives on the secondary FDC
+
+
+Configuration Data Structure
+----------------------------
+
+The configuration data is stored in the extension BIOS ROM starting from
+offset 1F80h.
+
+Here is the location and the purpose of the configuration data:
+
+Offset 1F80h, size 1 bytes:
+Checksum correction byte. Value of this byte is negative of the sum of the
+rest of bytes in 1F81h - 1FFFh range, so that the sum of the 1F80h - 1FFFh
+range equals zero.
+
+Offset 1F81h, size 32 bytes:
+Floppy drive configuration, 8 entries, 4 bytes each:
+	byte 0 - drive type:
+		0 - drive not present
+		1 - 360 KB, 5.25"
+		2 - 1.2 MB, 5.25"
+		3 - 720 KB, 3.5"
+		4 - 1.44 MB, 3.5"
+		6 - 2.88 MB, 3.5"
+	byte 1 - FDC number: 0 - Primary FDC; 1 - Secondary FDC
+	byte 2 - physical drive number, from 0 to 3
+	byte 3 - reserved, must be set to 0
+Notes:
+- Drive entries must be populated consecutively, without any holes (drive not
+  present entries)
+- When using the standard IBM PC twisted floppy cable, the drive after the
+  twist is the physical drive 0, and the drive before the twist is the physical
+  drive 1.
+
+Offset 1FA1h, size 8 bytes:
+FDC configuration, 2 entries (primary FDC and secondary FDC), 4 bytes each:
+	word 0 - FDC base address.
+		Normally 3F0h for the primary FDC and 370h for the secondary FDC
+	byte 2 - FDC interrupt (IRQ) number.
+		Normally 6 for the primary FDC
+	byte 3 - FDC DMA channel number.
+		Normally 2 for the primary FDC
+
+Offset 1FA9h, size 4 bytes:
+Pointer to floppy drive media state for drives 4-7 variables array.
+	word 0 - offset; default: 02C0h
+	word 2 - segment; default; 0000h
+
+Offset 1FADh, size 4 bytes:
+Pointer to current cylinder for drives 2-7 variables array:
+	word 0 - offset; default: 02C4h
+	word 2 - segment; default: 0000h
+
+Offset 1FB1h, size 4 bytes:
+Pointer to mode, motor state, and selected drive for the secondary FDC variable:
+	word 0 - offset; default: 02CAh
+	word 2 - segment; default: 0000h
+
+Offset 1FB5, size 2 bytes:
+Configuration prompt (Press F2...) delay in 55 ms units
+	word - default: 55 (approximately 3 seconds)
+
+Offset 1FB7, size 1 byte:
+Configuration flags
+	bit 0 - Use port 61h / bit 4 for delays (implemented on AT and Xi 8088)
+		default: 0 - Don't use port 61; for PC/XT class machines.
+	bit 1 - Display configuration prompt during extension ROM initialization
+		default: 0 - Don't display
+	bit 2 - Display configuration prompt on boot (INT 19h)
+		default: 0 - Display
+	bit 3 - Update BIOS equipment word during extension ROM initialization
+		default: 1 - Update
+	bit 4 - Update BIOS equipment word on boot (INT 19h)
+		default: 1 - Update
+	bit 5 - Enable builtin IPL
+		default: 1 - Enabled
+	bits 6 - 7 - Reserved, set to 0
+
+Offset 1FB8, size 3 bytes:
+Code to run relocated timer (IRQ0) handler. The second byte is also used to
+determine what interrupt number the default INT 08h handler should be
+relocated to. This is only used in configurations with two FDCs.
+	byte 0 - default: 0CDh (INT opcode)
+	byte 1 - default: 0AFh (interrupt 0AFh)
+	byte 2 - default: 0CFh (IRET opcode)
+
+Offset 1FBB, size 3 bytes;
+Code to run relocated INT 19h (boot) handler. The second byte is also used to
+determine what interrupt number the default INT 19h handler should be
+relocated to.
+	byte 0 - default: 0CDh (INT opcode)
+	byte 1 - default: 0AEh (interrupt 0AEh)
+	byte 2 - default: 0CFh (IRET opcode)
+
+
+Enabling SDP (Software Data Protection) feature
+-----------------------------------------------
+
+Atmel AT28C64B EEPROMs support the SDP feature which allows disabling
+EEPROM writes using a special sequence. It is recommended to enable this
+feature if you have this EEPROM type, as it will prevent accidential EEPROM
+modifications, while allowing the built-in configuration utility to modify
+the configuration without changing "EEPROM write protect" switch / jumper
+setting.
+
+Here is an example of enabling SDP feature using the DOS DEBUG command. Note
+that the first command (mov ax,e000) needs to be updated to reflect the segment
+address of the EEPROM, according to the configuration of the ISA FDC card.
+
+C:\>debug
+-a
+151D:0100 mov ax,e000
+151D:0103 mov ds,ax
+151D:0105 mov byte [1555],aa
+151D:010A mov byte [0aaa],55
+151D:010F mov byte [1555],a0
+151D:0114 xor cx,cx
+151D:0116 loop 116
+151D:0118 int 20
+-g
+
+Note: This command sequence is only supported on Atmel AT28C64B EEPROM, it
+won't work on other EEPROMs and will corrupt the EEPROM content instead.
+
+TODO
+====
+
+- Better check for HDD BIOS presence? (e.g. call INT 13h AH=15h)
+
+- Detect and initialize FDC controllers on initialization. Display a warning
+  message on timeout/controller not present.
+
+- Implement IRQ/DRQ sharing for primary FDC and secondary FDC.
+
+- Make the ROM PnP specs compliant?