Add POCSAG support (TX)

n2xdd · Jun 18, 2018 · 121e909 · 121e909
1 parent 82b62b9
commit 121e909
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Showing 23 changed files with 367 additions and 56 deletions.
diff --git a/ADF7021.cpp b/ADF7021.cpp
@@ -48,6 +48,7 @@ uint16_t           m_dmrDev;
 uint16_t           m_ysfDev;
 uint16_t           m_p25Dev;
 uint16_t           m_nxdnDev;
+uint16_t           m_pocsagDev;
 
 static void Send_AD7021_control_shift()
 {
@@ -186,7 +187,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   uint32_t ADF7021_REG13 = 0U;
   int32_t AFC_OFFSET = 0;
 
-  if(modemState != STATE_CWID)
+  if(modemState != STATE_CWID && modemState != STATE_POCSAG)
     m_modemState_prev = modemState;
 
   // Toggle CE pin for ADF7021 reset
@@ -226,6 +227,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
 
   switch (modemState) {
     case STATE_DSTAR:
+    case STATE_POCSAG:
       AFC_OFFSET = 0;
       break;
     case STATE_DMR:
@@ -314,6 +316,28 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
       ADF7021_REG2 |= (uint32_t) 0b111                     << 4;   // modulation (RC 4FSK)
       break;
 
+    case STATE_POCSAG:
+      // Dev: 4500 Hz, symb rate = 1200
+
+      ADF7021_REG3 = ADF7021_REG3_POCSAG;
+      ADF7021_REG10 = ADF7021_REG10_POCSAG;
+
+      ADF7021_REG4  = (uint32_t) 0b0100                     << 0;   // register 4
+      ADF7021_REG4 |= (uint32_t) 0b001                      << 4;   // demod mode, 2FSK
+      ADF7021_REG4 |= (uint32_t) 0b1                        << 7;
+      ADF7021_REG4 |= (uint32_t) 0b10                       << 8;
+      ADF7021_REG4 |= (uint32_t) ADF7021_DISC_BW_POCSAG     << 10;  // Disc BW
+      ADF7021_REG4 |= (uint32_t) ADF7021_POST_BW_POCSAG     << 20;  // Post dem BW
+      ADF7021_REG4 |= (uint32_t) 0b10                       << 30;  // IF filter (25 kHz)
+
+      // Register 13 not used with 2FSK
+      ADF7021_REG13 = (uint32_t) 0b1101                     << 0;   // register 13
+
+      ADF7021_REG2  = (uint32_t) 0b00                       << 28;  // clock normal
+      ADF7021_REG2 |= (uint32_t) (ADF7021_DEV_POCSAG / div2)<< 19;  // deviation
+      ADF7021_REG2 |= (uint32_t) 0b000                      << 4;   // modulation (2FSK)
+      break;
+
     case STATE_DSTAR:
       // Dev: 1200 Hz, symb rate = 4800
 
@@ -523,7 +547,7 @@ void CIO::ifConf(MMDVM_STATE modemState, bool reset)
   Send_AD7021_control();
 
 #if defined(DUPLEX)
-if(m_duplex && (modemState != STATE_CWID))
+if(m_duplex && (modemState != STATE_CWID && modemState != STATE_POCSAG))
   ifConf2(modemState);
 #endif
 }
@@ -888,7 +912,7 @@ void CIO::setPower(uint8_t power)
   m_power = power >> 2;
 }
 
-void CIO::setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, bool ysfLoDev)
+void CIO::setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, uint8_t pocsagTXLevel, bool ysfLoDev)
 {
   m_dstarDev = uint16_t((ADF7021_DEV_DSTAR * uint16_t(dstarTXLevel)) / 128U);
   m_dmrDev = uint16_t((ADF7021_DEV_DMR * uint16_t(dmrTXLevel)) / 128U);
@@ -900,6 +924,7 @@ void CIO::setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXL
 
   m_p25Dev = uint16_t((ADF7021_DEV_P25 * uint16_t(p25TXLevel)) / 128U);
   m_nxdnDev = uint16_t((ADF7021_DEV_NXDN * uint16_t(nxdnTXLevel)) / 128U);
+  m_pocsagDev = uint16_t((ADF7021_DEV_POCSAG * uint16_t(pocsagTXLevel)) / 128U);
 }
 
 void CIO::updateCal()
@@ -1011,6 +1036,11 @@ uint16_t CIO::devNXDN()
   return (uint16_t)((ADF7021_PFD * m_nxdnDev) / (f_div * 65536));
 }
 
+uint16_t CIO::devPOCSAG()
+{
+  return (uint16_t)((ADF7021_PFD * m_pocsagDev) / (f_div * 65536));
+}
+
 void CIO::printConf()
 {
   DEBUG1("MMDVM_HS FW configuration:");
@@ -1022,6 +1052,7 @@ void CIO::printConf()
   DEBUG2("YSF +1 sym dev (Hz):", devYSF());
   DEBUG2("P25 +1 sym dev (Hz):", devP25());
   DEBUG2("NXDN +1 sym dev (Hz):", devNXDN());
+  DEBUG2("POCSAG dev (Hz):", devPOCSAG());
 }
 
 #endif

diff --git a/ADF7021.h b/ADF7021.h
@@ -67,6 +67,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // DEMOD_CLK = 4.9152 MHz (DMR, YSF_L, P25)
 // DEMOD_CLK = 7.3728 MHz (YSF_H)
 // DEMOD CLK = 3.6864 MHz (NXDN)
+// DEMOD_CLK = 7.3728 MHz (POCSAG)
 #define ADF7021_PFD              3686400.0
 
 // PLL (REG 01)
@@ -86,6 +87,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DEV_P25          22U
 #endif
 #define ADF7021_DEV_NXDN         13U
+#define ADF7021_DEV_POCSAG       160U
 
 // TX/RX CLOCK register (REG 03)
 #define ADF7021_REG3_DSTAR       0x2A4C4193
@@ -102,6 +104,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG3_P25         0x2A4C80D3
 #define ADF7021_REG3_NXDN        0x2A4CC113
 #endif
+#define ADF7021_REG3_POCSAG      0x2A4F0093
 
 // Discriminator bandwith, demodulator (REG 04)
 // Bug in ADI evaluation software, use datasheet formula (4FSK)
@@ -111,13 +114,15 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DISC_BW_YSF_H    516U // K=28
 #define ADF7021_DISC_BW_P25      394U // K=32
 #define ADF7021_DISC_BW_NXDN     295U // K=32
+#define ADF7021_DISC_BW_POCSAG   406U // K=22
 
 // Post demodulator bandwith (REG 04)
 #define ADF7021_POST_BW_DSTAR    10U
 #define ADF7021_POST_BW_DMR      150U
 #define ADF7021_POST_BW_YSF      20U
 #define ADF7021_POST_BW_P25      6U
 #define ADF7021_POST_BW_NXDN     7U
+#define ADF7021_POST_BW_POCSAG   1U
 
 // IF filter (REG 05)
 #define ADF7021_REG5             0x000024F5
@@ -127,6 +132,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 
 // AFC configuration (REG 10)
 #define ADF7021_REG10_DSTAR      0x0C96473A
+#define ADF7021_REG10_POCSAG     0x1496473A
 
 #if defined(ADF7021_ENABLE_4FSK_AFC)
 #define ADF7021_REG10_DMR        0x01FE473A
@@ -162,6 +168,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 // DEMOD_CLK = 2.4576 MHz (DSTAR)
 // DEMOD_CLK = 6.1440 MHz (DMR, YSF_H, YSF_L, P25)
 // DEMOD_CLK = 3.0720 MHz (NXDN)
+// DEMOD_CLK = 6.1440 MHz (POCSAG)
 #define ADF7021_PFD              6144000.0
 
 // PLL (REG 01)
@@ -181,6 +188,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DEV_P25          13U
 #endif
 #define ADF7021_DEV_NXDN         8U
+#define ADF7021_DEV_POCSAG       96U
 
 // TX/RX CLOCK register (REG 03)
 #define ADF7021_REG3_DSTAR       0x29EC4153
@@ -197,6 +205,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_REG3_P25         0x29ECA093
 #define ADF7021_REG3_NXDN        0x29ECA113
 #endif
+#define ADF7021_REG3_POCSAG      0x29EE8093
 
 // Discriminator bandwith, demodulator (REG 04)
 // Bug in ADI evaluation software, use datasheet formula (4FSK)
@@ -206,13 +215,15 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 #define ADF7021_DISC_BW_YSF_H    430U // K=28
 #define ADF7021_DISC_BW_P25      493U // K=32
 #define ADF7021_DISC_BW_NXDN     246U // K=32
+#define ADF7021_DISC_BW_POCSAG   338U // K=22
 
 // Post demodulator bandwith (REG 04)
 #define ADF7021_POST_BW_DSTAR    10U
 #define ADF7021_POST_BW_DMR      150U
 #define ADF7021_POST_BW_YSF      20U
 #define ADF7021_POST_BW_P25      6U
 #define ADF7021_POST_BW_NXDN     8U
+#define ADF7021_POST_BW_POCSAG   1U
 
 // IF filter (REG 05)
 #define ADF7021_REG5             0x00001ED5
@@ -222,6 +233,7 @@ www.analog.com/media/en/technical-documentation/data-sheets/ADF7021.pdf
 
 // AFC (REG 10)
 #define ADF7021_REG10_DSTAR      0x0C96557A
+#define ADF7021_REG10_POCSAG     0x1496557A
 
 #if defined(ADF7021_ENABLE_4FSK_AFC)
 #define ADF7021_REG10_DMR        0x01FE557A

diff --git a/DMRDMOTX.cpp b/DMRDMOTX.cpp
@@ -36,7 +36,6 @@ m_poBuffer(),
 m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(240U),      // 200ms
-m_count(0U),
 m_delay(false),
 m_cal(false)
 {

diff --git a/DMRDMOTX.h b/DMRDMOTX.h
@@ -45,7 +45,6 @@ class CDMRDMOTX {
   uint16_t             m_poLen;
   uint16_t             m_poPtr;
   uint16_t             m_txDelay;
-  uint32_t             m_count;
   bool                 m_delay;
   bool                 m_cal;
 

diff --git a/DStarTX.cpp b/DStarTX.cpp
@@ -186,9 +186,8 @@ m_poBuffer(),
 m_poLen(0U),
 m_poPtr(0U),
 m_txDelay(60U),      // 100ms
-m_count(0U)
+m_delay(false)
 {
-
 }
 
 void CDStarTX::process()
@@ -201,7 +200,6 @@ void CDStarTX::process()
   if (type == DSTAR_HEADER && m_poLen == 0U) {
     if (!m_tx) {
       m_delay = true;
-      m_count = 0U;
       m_poLen = m_txDelay;
     } else {
       m_delay = false;
@@ -228,8 +226,6 @@ void CDStarTX::process()
 
   if (type == DSTAR_DATA && m_poLen == 0U) {
     m_delay = false;
-    if (!m_tx)
-      m_count = 0U;
 
     // Pop the type byte off
     m_buffer.get();

diff --git a/DStarTX.h b/DStarTX.h
@@ -42,7 +42,6 @@ class CDStarTX {
   uint16_t             m_poLen;
   uint16_t             m_poPtr;
   uint16_t             m_txDelay;          // In bytes
-  uint32_t             m_count;
   bool                 m_delay;
 
   void txHeader(const uint8_t* in, uint8_t* out) const;

diff --git a/Globals.h b/Globals.h
@@ -40,6 +40,7 @@ enum MMDVM_STATE {
   STATE_YSF       = 3,
   STATE_P25       = 4,
   STATE_NXDN      = 5,
+  STATE_POCSAG    = 6,
 
   // Dummy states start at 90
   STATE_DMRDMO1K  = 92,
@@ -75,6 +76,7 @@ const uint8_t  MARK_NONE  = 0x00U;
 #include "P25TX.h"
 #include "NXDNRX.h"
 #include "NXDNTX.h"
+#include "POCSAGTX.h"
 #include "CWIdTX.h"
 #include "CalRSSI.h"
 #include "CalDMR.h"
@@ -89,6 +91,8 @@ extern MMDVM_STATE m_calState;
 extern MMDVM_STATE m_modemState_prev;
 
 extern bool m_cwid_state;
+extern bool m_pocsag_state;
+
 extern uint8_t m_cwIdTXLevel;
 
 extern uint32_t m_modeTimerCnt;
@@ -98,6 +102,7 @@ extern bool m_dmrEnable;
 extern bool m_ysfEnable;
 extern bool m_p25Enable;
 extern bool m_nxdnEnable;
+extern bool m_pocsagEnable;
 
 extern bool m_duplex;
 
@@ -130,6 +135,8 @@ extern CP25TX p25TX;
 extern CNXDNRX nxdnRX;
 extern CNXDNTX nxdnTX;
 
+extern CPOCSAGTX pocsagTX;
+
 extern CCalDMR  calDMR;
 
 #if defined(SEND_RSSI_DATA)

diff --git a/IO.cpp b/IO.cpp
@@ -48,6 +48,7 @@ m_watchdog(0U)
   YSF_pin(LOW);
   P25_pin(LOW);
   NXDN_pin(LOW);
+  POCSAG_pin(LOW);
   COS_pin(LOW);
   DEB_pin(LOW);
 
@@ -85,6 +86,7 @@ void CIO::selfTest()
       YSF_pin(ledValue);
       P25_pin(ledValue);
       NXDN_pin(ledValue);
+      POCSAG_pin(ledValue);
       COS_pin(ledValue);
 
       blinks++;
@@ -106,7 +108,7 @@ void CIO::process()
   if (m_started) {
     // Two seconds timeout
     if (m_watchdog >= 19200U) {
-      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF ||  m_modemState == STATE_P25 ||  m_modemState == STATE_NXDN) {
+      if (m_modemState == STATE_DSTAR || m_modemState == STATE_DMR || m_modemState == STATE_YSF || m_modemState == STATE_P25 || m_modemState == STATE_NXDN) {
         m_modemState = STATE_IDLE;
         setMode(m_modemState);
       }
@@ -139,6 +141,11 @@ void CIO::process()
       // Restoring previous mode
       io.ifConf(m_modemState_prev, true);
     }
+    if(m_pocsag_state) { // check for POCSAG end of transmission
+      m_pocsag_state = false;
+      // Restoring previous mode
+      io.ifConf(m_modemState_prev, true);
+    }
     setRX(false);
   }
 
@@ -157,7 +164,7 @@ void CIO::process()
 
   if(m_modeTimerCnt >= scantime) {
     m_modeTimerCnt = 0U;
-    if( (m_modemState == STATE_IDLE) && (m_scanPauseCnt == 0U) && m_scanEnable && !m_cwid_state) {
+    if( (m_modemState == STATE_IDLE) && (m_scanPauseCnt == 0U) && m_scanEnable && !m_cwid_state && !m_pocsag_state) {
       m_scanPos = (m_scanPos + 1U) % m_TotalModes;
       #if !defined(QUIET_MODE_LEDS)
       setMode(m_Modes[m_scanPos]);
@@ -306,7 +313,8 @@ void CIO::setMode(MMDVM_STATE modemState)
   DMR_pin(modemState   == STATE_DMR);
   YSF_pin(modemState   == STATE_YSF);
   P25_pin(modemState   == STATE_P25);
-  NXDN_pin(modemState   == STATE_NXDN);
+  NXDN_pin(modemState  == STATE_NXDN);
+  POCSAG_pin(modemState  == STATE_POCSAG);
 }
 
 void CIO::setDecode(bool dcd)

diff --git a/IO.h b/IO.h
@@ -76,6 +76,7 @@ class CIO {
   void      YSF_pin(bool on);
   void      P25_pin(bool on);
   void      NXDN_pin(bool on);
+  void      POCSAG_pin(bool on);
   void      COS_pin(bool on);
   void      interrupt(void);
 #if defined(DUPLEX)
@@ -110,7 +111,7 @@ class CIO {
 #endif
   void      start(void);
   void      startInt(void);
-  void      setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, bool ysfLoDev);
+  void      setDeviations(uint8_t dstarTXLevel, uint8_t dmrTXLevel, uint8_t ysfTXLevel, uint8_t p25TXLevel, uint8_t nxdnTXLevel, uint8_t pocsagTXLevel, bool ysfLoDev);
   void      updateCal(void);
 
 #if defined(SEND_RSSI_DATA)
@@ -131,6 +132,7 @@ class CIO {
   uint16_t  devYSF(void);
   uint16_t  devP25(void);
   uint16_t  devNXDN(void);
+  uint16_t  devPOCSAG(void);
   void      printConf();
 #endif
 

diff --git a/IOArduino.cpp b/IOArduino.cpp
@@ -316,6 +316,11 @@ void CIO::NXDN_pin(bool on)
   digitalWrite(PIN_NXDN_LED, on ? HIGH : LOW);
 }
 
+void CIO::POCSAG_pin(bool on)
+{
+  // TODO: add a LED pin for POCSAG mode
+}
+
 void CIO::PTT_pin(bool on) 
 {
   digitalWrite(PIN_PTT_LED, on ? HIGH : LOW);

diff --git a/IOSTM.cpp b/IOSTM.cpp
@@ -647,6 +647,11 @@ void CIO::NXDN_pin(bool on)
   GPIO_WriteBit(PORT_NXDN_LED, PIN_NXDN_LED, on ? Bit_SET : Bit_RESET);
 }
 
+void CIO::POCSAG_pin(bool on)
+{
+  // TODO: add a LED pin for POCSAG mode
+}
+
 void CIO::PTT_pin(bool on)
 {
   GPIO_WriteBit(PORT_PTT_LED, PIN_PTT_LED, on ? Bit_SET : Bit_RESET);