Updated the issues #12
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Report Issues with RISC-V Instruction Simulation and Validation
Overview: This pull request aims to highlight two critical issues in the current RISC-V instruction simulation within the application:
Instruction Storage in Memory: The simulation currently does not accurately represent the process of storing RISC-V instructions in the instruction memory before they are executed. This means that instructions are not being stored properly, leading to incorrect execution behavior.
Lack of Validation: There is no validation mechanism in place for identifying incorrect instructions. Specifically, there is no linter or error-checking functionality to catch errors related to wrong instructions or improper argument values provided for those instructions.
By bringing these issues to attention, I hope to facilitate further discussion and potential solutions to enhance the accuracy and reliability of the RISC-V instruction simulation.