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masterhoumasterhou
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make a 16x16 pixel version
1 parent 684b4ef commit cbe98c5

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3 files changed

+71
-49
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3 files changed

+71
-49
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‎snake.v

+53-31
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,22 @@ localparam None_Color = {4'd15, 4'd15, 4'd15},
2424
Body_Color = {4'd09, 4'd15, 4'd00},
2525
Brick_Color ={4'd05, 4'd05, 4'd07},
2626
Apple_Color ={4'd15, 4'd00, 4'd00},
27-
Score_Color ={4'd08, 4'd08, 4'h15},
28-
HiSco_Color ={4'd15, 4'd08, 4'h00};
29-
30-
localparam Row = 5'd25, Col=5'd19;
31-
localparam Key_Left=4'h2, Key_Right=4'h4, Key_Down=4'h3, Key_Up=4'h7;
32-
//localparam N=4; // latency
27+
Score_Color ={4'd08, 4'd08, 4'd15},
28+
HiSco_Color ={4'd15, 4'd08, 4'd00};
29+
`define HD
30+
`ifdef HD
31+
localparam D=5, P=4, S=2;
32+
`else
33+
localparam D=4, P=5, S=1;
34+
`endif
35+
localparam Row = 5'd25*S, Col=5'd19*S;
36+
localparam Row_1 = Row-1, Col_1=Col-1;
3337

34-
reg[11:0] score, hi_score;
38+
localparam Key_Left=4'h2, Key_Right=4'h4, Key_Down=4'h3, Key_Up=4'h7;
3539

40+
///////////////////////////////////
3641
// data and video buffer
37-
reg[8:0] raddr, waddr;
42+
reg[10:0] raddr, waddr;
3843
reg[3:0] vdata;
3944
wire[3:0] vout;
4045
vram u_vram(
@@ -50,20 +55,26 @@ vram u_vram(
5055
.q_b (vout)
5156
);
5257

58+
///////////////////////////////////
59+
5360
reg[1:0] head_dir;
54-
reg[4:0] head_pos_x, head_pos_y;
55-
reg[4:0] tail_pos_x, tail_pos_y;
56-
reg[4:0] appl_pos_x, appl_pos_y;
61+
reg[D:0] head_pos_x, head_pos_y;
62+
reg[D:0] tail_pos_x, tail_pos_y;
63+
reg[D:0] appl_pos_x, appl_pos_y;
64+
reg[5:0] speed_cnt;
65+
reg[11:0] score, hi_score;
66+
67+
///////////////////////////////////
5768

5869
wire[3:0] code;
5970
wire keydown, scan_clk;
6071
keypad4x4 key(v_cnt, rst, row, col, code, keydown, scan_clk);
6172

73+
///////////////////////////////////
74+
6275
wire[3:0] LED[7:0];
6376
led8 led(scan_clk, rst, LED[0], LED[1], LED[2], LED[3], LED[4], LED[5], LED[6], LED[7], LEDOut, DigitSelect);
6477

65-
reg[4:0] speed_cnt;
66-
6778
// debug info led /////////////////
6879
//assign Light[0] = ~keydown;
6980
//assign Light[1] = keydown;
@@ -76,31 +87,41 @@ assign LED[2] = score[ 3:0];
7687

7788
wire[7:0] randq;
7889
LFSR8_11D LFSR8_11D(clk, rst, randq);
79-
wire[4:0] rand_x = randq[3:0]+randq[6:4]; // 16+8=24
80-
wire[4:0] rand_y = randq[7:4]+randq[1:0]; // 16+3=19
90+
91+
`ifdef HD
92+
wire[D:0] rand_x = randq[4:0]+randq[7:4]; // 32+16=48
93+
wire[D:0] rand_y = randq[7:3]+randq[1:0]; // 32+3=38
94+
`else
95+
wire[D:0] rand_x = randq[3:0]+randq[6:4]; // 16+8=24
96+
wire[D:0] rand_y = randq[7:4]+randq[1:0]; // 16+3=19
97+
`endif
98+
99+
///////////////////////////////////
81100

82101
wire[1:0] frame_sync;
83102
assign frame_sync[0] = v_cnt==1 && h_cnt==0;
84103
assign frame_sync[1] = v_cnt==1 && h_cnt==2;
85104

105+
///////////////////////////////////
106+
86107
reg[3:0] ram_state;
87108
localparam ram_clr=0, ram_gen_apple=1, ram_set_apple=2, ram_set_head=3,
88-
ram_logic=4, ram_check=5, ram_clr_tail=6, ram_start=7,
89-
ram_gen_apple_d=8, ram_check_d=9, ram_clr_tail_d=10;
109+
ram_logic=4, ram_check=5, ram_clr_tail=6, ram_start=7,
110+
ram_gen_apple_d=8, ram_check_d=9, ram_clr_tail_d=10;
90111

91112
always @(posedge clk or negedge rst)
92113
if(!rst) begin
93114
hi_score <= 1'b0;
94-
{appl_pos_x, appl_pos_y} <= {5'd10, 5'd2};
95-
{tail_pos_x, tail_pos_y} <= {5'd1, 5'd2};
115+
appl_pos_x<=4'd9; appl_pos_y<=4'd2;
116+
tail_pos_x<=4'd1; tail_pos_y<=4'd2;
96117
ram_state <= ram_start;
97118
end
98119
else if(ram_state==ram_start) begin // reset screen
99120
speed_cnt <= 1'b0;
100121
score <= 1'b0;
101-
vdata <= {Right, None};
102-
waddr <= 8'd0;
103-
raddr <= 8'd0;
122+
vdata <= 1'b0;
123+
waddr <= 1'b0;
124+
raddr <= 1'b0;
104125
ram_state <= ram_clr;
105126
end
106127
else if(ram_state==ram_clr) begin // reset screen
@@ -139,8 +160,8 @@ always @(posedge clk or negedge rst)
139160
ram_state <= ram_set_head; // save head turn direct
140161
else if(frame_sync[1]) // new frame begin, start snake speed count
141162
speed_cnt <= speed_cnt+1'b1;
142-
if(x[9:5]<Row)
143-
raddr <= Row*y[9:5] + x[9:5]; // read cell(32*32 pixel) for graphic render
163+
if(x[9:P]<Row)
164+
raddr <= Row*y[9:P] + x[9:P]; // read cell(32*32 pixel) for graphic render
144165
end
145166
else if(ram_state==ram_check_d) // vram read latecy 2 clk
146167
ram_state <= ram_check;
@@ -173,8 +194,9 @@ always @(posedge clk or negedge rst)
173194
wire clk_move= speed_cnt==Speed;
174195
// go ahead, move head position, before check collision one clock
175196
always @(posedge clk_move or negedge rst)
176-
if(!rst)
177-
{head_pos_x, head_pos_y} <= {5'd1, 5'd2};
197+
if(!rst) begin
198+
head_pos_x<=4'd1; head_pos_y<=4'd2;
199+
end
178200
else
179201
move(head_dir, head_pos_x, head_pos_y);
180202

@@ -193,12 +215,12 @@ always @(posedge keydown or negedge rst)
193215

194216
task move;
195217
input wire[1:0] dir;
196-
inout reg[4:0] px, py;
218+
inout reg[D:0] px, py;
197219
case(dir) // dir
198-
Right: px <= px<5'd24 ? px + 1'b1 : 5'd00;
199-
Left: px <= px>5'd00 ? px - 1'b1 : 5'd24;
200-
Up: py <= py>5'd00 ? py - 1'b1 : 5'd18;
201-
Down: py <= py<5'd18 ? py + 1'b1 : 5'd00;
220+
Right: px <= px<Row_1 ? px + 1'b1 : 1'b00;
221+
Left: px <= px>1'b00 ? px - 1'b1 : Row_1;
222+
Up: py <= py>1'b00 ? py - 1'b1 : Col_1;
223+
Down: py <= py<Col_1 ? py + 1'b1 : 1'b00;
202224
endcase
203225
endtask
204226

‎text.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ always @(posedge clk or negedge rst)
4040
dout <= 1'b0;
4141
end
4242

43-
always @(rom_adress)
43+
always @(rom_adress or y or posy)
4444
if(y >= posy && y < posy + `CHAR_HEIGHT)
4545
rom_adr <= rom_adress + (y-posy);
4646

@@ -54,7 +54,7 @@ module block #(parameter N=4)
5454
input wire[9:0] posx, posy,
5555
input wire[10:0] x, y,
5656
input wire[11:0] number,
57-
output wire do
57+
output wire dout
5858
);
5959
`include "para_define.v"
6060

@@ -65,7 +65,7 @@ reg[3:0] char[0:4];
6565
assign xx = (x-posx);
6666
assign i = xx[9:5]<N ? xx[9:5] : 0;
6767
assign poxx = posx + `CHAR_WIDETH*i;
68-
text text(clk, rst, rom_address, rom_data, poxx, posy, x, y, char[i], do);
68+
text text(clk, rst, rom_address, rom_data, poxx, posy, x, y, char[i], dout);
6969

7070
always @(number) begin
7171
char[0] <= number / 1000;

‎vram.v

+15-15
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,8 @@ module vram (
4848
q_a,
4949
q_b);
5050

51-
input [8:0] address_a;
52-
input [8:0] address_b;
51+
input [10:0] address_a;
52+
input [10:0] address_b;
5353
input clock_a;
5454
input clock_b;
5555
input [3:0] data_a;
@@ -106,8 +106,8 @@ module vram (
106106
altsyncram_component.indata_reg_b = "CLOCK1",
107107
altsyncram_component.intended_device_family = "Cyclone III",
108108
altsyncram_component.lpm_type = "altsyncram",
109-
altsyncram_component.numwords_a = 512,
110-
altsyncram_component.numwords_b = 512,
109+
altsyncram_component.numwords_a = 2048,
110+
altsyncram_component.numwords_b = 2048,
111111
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
112112
altsyncram_component.outdata_aclr_a = "NONE",
113113
altsyncram_component.outdata_aclr_b = "NONE",
@@ -117,8 +117,8 @@ module vram (
117117
altsyncram_component.ram_block_type = "M9K",
118118
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
119119
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
120-
altsyncram_component.widthad_a = 9,
121-
altsyncram_component.widthad_b = 9,
120+
altsyncram_component.widthad_a = 11,
121+
altsyncram_component.widthad_b = 11,
122122
altsyncram_component.width_a = 4,
123123
altsyncram_component.width_b = 4,
124124
altsyncram_component.width_byteena_a = 1,
@@ -161,7 +161,7 @@ endmodule
161161
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
162162
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
163163
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
164-
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
164+
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
165165
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
166166
// Retrieval info: PRIVATE: MIFfilename STRING ""
167167
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
@@ -199,8 +199,8 @@ endmodule
199199
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
200200
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
201201
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
202-
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
203-
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
202+
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
203+
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
204204
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
205205
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
206206
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
@@ -210,15 +210,15 @@ endmodule
210210
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
211211
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
212212
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
213-
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
214-
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
213+
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
214+
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
215215
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
216216
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "4"
217217
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
218218
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
219219
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
220-
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
221-
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
220+
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
221+
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
222222
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
223223
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
224224
// Retrieval info: USED_PORT: data_a 0 0 4 0 INPUT NODEFVAL "data_a[3..0]"
@@ -227,8 +227,8 @@ endmodule
227227
// Retrieval info: USED_PORT: q_b 0 0 4 0 OUTPUT NODEFVAL "q_b[3..0]"
228228
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
229229
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
230-
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
231-
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
230+
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
231+
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
232232
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
233233
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
234234
// Retrieval info: CONNECT: @data_a 0 0 4 0 data_a 0 0 4 0

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