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masterhoumasterhou
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add score and hi-score
1 parent da1af4d commit 684b4ef

11 files changed

+1233
-149
lines changed

‎Snake_fpga.qsf

+24-4
Original file line numberDiff line numberDiff line change
@@ -87,8 +87,7 @@ set_location_assignment PIN_162 -to row[3]
8787
set_location_assignment PIN_164 -to row[2]
8888
set_location_assignment PIN_166 -to row[1]
8989
set_location_assignment PIN_167 -to row[0]
90-
set_location_assignment PIN_120 -to sw_brick
91-
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
90+
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
9291
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
9392
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
9493
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
@@ -119,7 +118,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDOut[0]
119118
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
120119
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to hsync
121120
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst
122-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sw_brick
123121
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
124122
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
125123
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
@@ -150,11 +148,33 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Light[3]
150148
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Light[2]
151149
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Light[1]
152150
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Light[0]
153-
set_global_assignment -name CDF_FILE output_files/Snake_fpga.cdf
151+
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
152+
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
153+
set_location_assignment PIN_120 -to Speed[5]
154+
set_location_assignment PIN_126 -to Speed[4]
155+
set_location_assignment PIN_127 -to Speed[3]
156+
set_location_assignment PIN_128 -to Speed[2]
157+
set_location_assignment PIN_131 -to Speed[1]
158+
set_location_assignment PIN_132 -to Speed[0]
159+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[4]
160+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[3]
161+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[2]
162+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[1]
163+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[0]
164+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to Speed[5]
165+
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
166+
set_global_assignment -name ENABLE_NCE_PIN OFF
167+
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
168+
set_global_assignment -name VERILOG_FILE I2C_Controller.v
169+
set_global_assignment -name VERILOG_FILE para_define.v
154170
set_global_assignment -name VERILOG_FILE keypad.v
155171
set_global_assignment -name VERILOG_FILE snake.v
156172
set_global_assignment -name VERILOG_FILE vga.v
157173
set_global_assignment -name VERILOG_FILE led8.v
158174
set_global_assignment -name VERILOG_FILE LFSR8_11D.v
159175
set_global_assignment -name QIP_FILE vram.qip
176+
set_global_assignment -name VERILOG_FILE sdram.v
177+
set_global_assignment -name QIP_FILE chrom.qip
178+
set_global_assignment -name VERILOG_FILE text.v
179+
set_global_assignment -name VERILOG_FILE I2C_NS2009.v
160180
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

‎chrom.qip

+3
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
2+
set_global_assignment -name IP_TOOL_VERSION "13.1"
3+
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "chrom.v"]

‎chrom.v

+161
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,161 @@
1+
// megafunction wizard: %ROM: 1-PORT%
2+
// GENERATION: STANDARD
3+
// VERSION: WM1.0
4+
// MODULE: altsyncram
5+
6+
// ============================================================
7+
// File Name: chrom.v
8+
// Megafunction Name(s):
9+
// altsyncram
10+
//
11+
// Simulation Library Files(s):
12+
// altera_mf
13+
// ============================================================
14+
// ************************************************************
15+
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16+
//
17+
// 13.1.0 Build 162 10/23/2013 SJ Full Version
18+
// ************************************************************
19+
20+
21+
//Copyright (C) 1991-2013 Altera Corporation
22+
//Your use of Altera Corporation's design tools, logic functions
23+
//and other software and tools, and its AMPP partner logic
24+
//functions, and any output files from any of the foregoing
25+
//(including device programming or simulation files), and any
26+
//associated documentation or information are expressly subject
27+
//to the terms and conditions of the Altera Program License
28+
//Subscription Agreement, Altera MegaCore Function License
29+
//Agreement, or other applicable license agreement, including,
30+
//without limitation, that your use is for the sole purpose of
31+
//programming logic devices manufactured by Altera and sold by
32+
//Altera or its authorized distributors. Please refer to the
33+
//applicable agreement for further details.
34+
35+
36+
// synopsys translate_off
37+
`timescale 1 ps / 1 ps
38+
// synopsys translate_on
39+
module chrom (
40+
address,
41+
clock,
42+
q);
43+
44+
input [9:0] address;
45+
input clock;
46+
output [31:0] q;
47+
`ifndef ALTERA_RESERVED_QIS
48+
// synopsys translate_off
49+
`endif
50+
tri1 clock;
51+
`ifndef ALTERA_RESERVED_QIS
52+
// synopsys translate_on
53+
`endif
54+
55+
wire [31:0] sub_wire0;
56+
wire [31:0] q = sub_wire0[31:0];
57+
58+
altsyncram altsyncram_component (
59+
.address_a (address),
60+
.clock0 (clock),
61+
.q_a (sub_wire0),
62+
.aclr0 (1'b0),
63+
.aclr1 (1'b0),
64+
.address_b (1'b1),
65+
.addressstall_a (1'b0),
66+
.addressstall_b (1'b0),
67+
.byteena_a (1'b1),
68+
.byteena_b (1'b1),
69+
.clock1 (1'b1),
70+
.clocken0 (1'b1),
71+
.clocken1 (1'b1),
72+
.clocken2 (1'b1),
73+
.clocken3 (1'b1),
74+
.data_a ({32{1'b1}}),
75+
.data_b (1'b1),
76+
.eccstatus (),
77+
.q_b (),
78+
.rden_a (1'b1),
79+
.rden_b (1'b1),
80+
.wren_a (1'b0),
81+
.wren_b (1'b0));
82+
defparam
83+
altsyncram_component.address_aclr_a = "NONE",
84+
altsyncram_component.clock_enable_input_a = "BYPASS",
85+
altsyncram_component.clock_enable_output_a = "BYPASS",
86+
altsyncram_component.init_file = "rom_init.mif",
87+
altsyncram_component.intended_device_family = "Cyclone III",
88+
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
89+
altsyncram_component.lpm_type = "altsyncram",
90+
altsyncram_component.numwords_a = 1024,
91+
altsyncram_component.operation_mode = "ROM",
92+
altsyncram_component.outdata_aclr_a = "NONE",
93+
altsyncram_component.outdata_reg_a = "UNREGISTERED",
94+
altsyncram_component.ram_block_type = "M9K",
95+
altsyncram_component.widthad_a = 10,
96+
altsyncram_component.width_a = 32,
97+
altsyncram_component.width_byteena_a = 1;
98+
99+
100+
endmodule
101+
102+
// ============================================================
103+
// CNX file retrieval info
104+
// ============================================================
105+
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
106+
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
107+
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
108+
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
109+
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
110+
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
111+
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
112+
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
113+
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
114+
// Retrieval info: PRIVATE: Clken NUMERIC "0"
115+
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
116+
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
117+
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
118+
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
119+
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
120+
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
121+
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
122+
// Retrieval info: PRIVATE: MIFfilename STRING "rom_init.mif"
123+
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
124+
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
125+
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
126+
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
127+
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
128+
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
129+
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
130+
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
131+
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
132+
// Retrieval info: PRIVATE: rden NUMERIC "0"
133+
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
134+
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
135+
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
136+
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
137+
// Retrieval info: CONSTANT: INIT_FILE STRING "rom_init.mif"
138+
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
139+
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
140+
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
141+
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
142+
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
143+
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
144+
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
145+
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
146+
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
147+
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
148+
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
149+
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
150+
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
151+
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
152+
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
153+
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
154+
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
155+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom.v TRUE
156+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom.inc FALSE
157+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom.cmp FALSE
158+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom.bsf FALSE
159+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom_inst.v FALSE
160+
// Retrieval info: GEN_FILE: TYPE_NORMAL chrom_bb.v FALSE
161+
// Retrieval info: LIB_FILE: altera_mf

‎keypad.v

+3-3
Original file line numberDiff line numberDiff line change
@@ -7,14 +7,14 @@ module keypad4x4(
77
output scan_clk
88
);
99

10-
reg[18:0] cnt;
10+
reg[10:0] cnt;
1111
reg[3:0] rowdown;
1212

1313
always @(posedge clk or negedge rst)
1414
if(!rst) cnt<=1'b0;
1515
else cnt <= cnt + 1'b1;
1616

17-
wire[1:0] index = cnt[18:17];
17+
wire[1:0] index = cnt[10:9];
1818
always @(posedge clk or negedge rst) begin
1919
if(!rst) col = 4'b0000;
2020
else
@@ -27,7 +27,7 @@ always @(posedge clk or negedge rst) begin
2727
end
2828

2929
assign keydown = ~(rowdown==2'b00);
30-
assign scan_clk = cnt[14];
30+
assign scan_clk = cnt[4];
3131

3232
always @(posedge scan_clk or negedge rst)
3333
if(!rst) code<=4'h0;

‎output_files/Snake_fpga.sof

0 Bytes
Binary file not shown.

‎para_define.v

+22
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
2+
// char bitmap address, size 32*64
3+
`define CHAR_WIDETH 6'd32
4+
`define CHAR_HEIGHT 7'd64
5+
6+
//0-9
7+
`define CHAR_0 (10'd64 * 10'd0)
8+
`define CHAR_1 (10'd64 * 10'd1)
9+
`define CHAR_2 (10'd64 * 10'd2)
10+
`define CHAR_3 (10'd64 * 10'd3)
11+
`define CHAR_4 (10'd64 * 10'd4)
12+
`define CHAR_5 (10'd64 * 10'd5)
13+
`define CHAR_6 (10'd64 * 10'd6)
14+
`define CHAR_7 (10'd64 * 10'd7)
15+
`define CHAR_8 (10'd64 * 10'd8)
16+
`define CHAR_9 (10'd64 * 10'd9)
17+
18+
//
19+
`define CHAR_mh (10'd64 * 10'd10) //':'
20+
21+
22+

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