Merge pull request #702 from ezchi/ezchi/fix-indent-level-variable-na…

…me-for-verilog-mode Fix indent level variable name for verilog-mode
manateelazycat · Aug 26, 2023 · 16670a0 · 16670a0
2 parents 6807fd4 + ba33e27
commit 16670a0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/lsp-bridge.el b/lsp-bridge.el
@@ -593,7 +593,7 @@ you can customize `lsp-bridge-get-workspace-folder' to return workspace folder p
     (yaml-mode                  . yaml-indent-offset) ; YAML
     (hack-mode                  . hack-indent-offset) ; Hack
     (kotlin-mode                . c-basic-offset)     ; Kotlin
-    (verilog-mode               . vhdl-indent-level)  ; Verilog
+    (verilog-mode               . verilog-indent-level)  ; Verilog
     (vhdl-mode                  . vhdl-basic-offset)  ; VHDL
     (go-mode                    . c-basic-offset)     ;Golang
     (go-ts-mode                 . c-basic-offset)     ;Golang