kasli_i2c: implement destination-aware EEPROM access for DRTIO

Signed-off-by: Florian Agbuya <[email protected]>

Author: fsagbuya

artiq/coredevice/kasli_i2c.py

@@ -25,29 +25,32 @@
 
 
 class KasliEEPROM:
-    def __init__(self, dmgr, port, address=0xa0, busno=0,
+    def __init__(self, dmgr, port, address=0xa0, busno=0, destination=0,
             core_device="core", sw0_device="i2c_switch0", sw1_device="i2c_switch1"):
         self.core = dmgr.get(core_device)
         self.sw0 = dmgr.get(sw0_device)
         self.sw1 = dmgr.get(sw1_device)
-        self.busno = busno
+        self.busno = (destination << 16) | (busno & 0xFF)
         self.port = port_mapping[port]
         self.address = address  # i2c 8 bit
 
     @kernel
     def select(self):
-        mask = 1 << self.port
-        if self.port < 8:
-            self.sw0.set(self.port)
-            self.sw1.unset()
-        else:
-            self.sw0.unset()
-            self.sw1.set(self.port - 8)
+        # Skip master-side switch operations for satellite EEPROMs
+        if (self.busno >> 16) == 0:
+            mask = 1 << self.port
+            if self.port < 8:
+                self.sw0.set(self.port)
+                self.sw1.unset()
+            else:
+                self.sw0.unset()
+                self.sw1.set(self.port - 8)
 
     @kernel
     def deselect(self):
-        self.sw0.unset()
-        self.sw1.unset()
+        if (self.busno >> 16) == 0:
+            self.sw0.unset()
+            self.sw1.unset()
 
     @kernel
     def write_i32(self, addr, value):