dma: report last write to FIFO

occheung · sbourdeauducq · commit 8bd03f5bb413 · 2025-03-03T15:55:16.000+08:00
diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py
@@ -66,6 +66,7 @@ def __init__(self, bus, cpu_dw):
             self.source.stb.eq(bus.ack),
 
             self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)),
+            self.source.last.eq(self.sink.eop | last),
             self.source.eop.eq(self.sink.eop),
         ]
 

Original file line number	Diff line number	Diff line change
`@@ -66,6 +66,7 @@ def __init__(self, bus, cpu_dw):`
`66`	`66`	`self.source.stb.eq(bus.ack),`
`67`	`67`
`68`	`68`	`self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)),`
	`69`	`+ self.source.last.eq(self.sink.eop \| last),`
`69`	`70`	`self.source.eop.eq(self.sink.eop),`
`70`	`71`	`]`
`71`	`72`