Merge branch 'release-1.1'

.gitattributes

@@ -1,2 +1,5 @@
 # Convert line endings for text files on Windows
 * text=auto
+
+# Prevent the GitHub parser from ignoring the "tools" directory contents
+/tools/* linguist-vendored=false

LICENSE.md

@@ -1,4 +1,4 @@
-Copyright (c) 2016 by Alex I. Kuznetsov
+Copyright (c) 2016-2019 by Alex I. Kuznetsov
 
 Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
 

doc/src/trm/frontmatter.tex

@@ -15,7 +15,7 @@
 	\Large a lightweight open source 32-bit CPU core\par
 	\LARGE \textbf{Technical Reference Manual}\par
 	\vspace{1.2\onelineskip}
-	\large Version 1.0\par
+	\large Version 1.1\par
 	\vspace*{4\onelineskip}
 	\end{center}
 	\vspace*{\fill}
@@ -34,7 +34,7 @@
 
 \vspace*{\fill}
 
-Copyright \textcopyright{} 2016 by Alex I. Kuznetsov.
+Copyright \textcopyright{} 2016--2019 by Alex I. Kuznetsov.
 
 The entire \lxp{} IP core package, including the synthesizable RTL description, verification environment, documentation and software tools, is distributed under the terms of the MIT license reproduced below:
 
@@ -46,8 +46,6 @@
 
 \vspace{4\baselineskip}
 
-Altera and Cyclone are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.
-
 Mentor Graphics and ModelSim are trademarks of Mentor Graphics Corporation.
 
 Microsemi and IGLOO are trademarks of Microsemi Corporation.

doc/src/trm/preamble.tex

@@ -1,4 +1,5 @@
 \usepackage{microtype}
+\usepackage{graphicx}
 \usepackage{alltt}
 \usepackage{amsmath}
 \usepackage[charter]{mathdesign}

misc/highlight/notepad++/LXP32Assembly.xml

@@ -1,5 +1,5 @@
 <NotepadPlus>
-    <UserLang name="LXP32 Assembly" ext="asm" udlVersion="2.1">
+    <UserLang name="LXP32 Assembly" ext="asm inc" udlVersion="2.1">
         <Settings>
             <Global caseIgnored="no" allowFoldOfComments="yes" foldCompact="no" forcePureLC="0" decimalSeparator="0" />
             <Prefix Keywords1="no" Keywords2="no" Keywords3="no" Keywords4="no" Keywords5="no" Keywords6="no" Keywords7="no" Keywords8="no" />
@@ -24,9 +24,9 @@
             <Keywords name="Folders in comment, open"></Keywords>
             <Keywords name="Folders in comment, middle"></Keywords>
             <Keywords name="Folders in comment, close"></Keywords>
-            <Keywords name="Keywords1">add and call cjmpe cjmpne cjmpsg cjmpsge cjmpsl cjmpsle cjmpug cjmpuge cjmpul cjmpule divs divu hlt jmp iret lc lsb lub lw mods modu mov mul nop not or ret sb sl srs sru sub sw xor</Keywords>
+            <Keywords name="Keywords1">add and call cjmpe cjmpne cjmpsg cjmpsge cjmpsl cjmpsle cjmpug cjmpuge cjmpul cjmpule divs divu hlt jmp iret lc lcs lsb lub lw mods modu mov mul neg nop not or ret sb sl srs sru sub sw xor</Keywords>
             <Keywords name="Keywords2">cr irp iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 r63 r64 r65 r66 r67 r68 r69 r70 r71 r72 r73 r74 r75 r76 r77 r78 r79 r80 r81 r82 r83 r84 r85 r86 r87 r88 r89 r90 r91 r92 r93 r94 r95 r96 r97 r98 r99 r100 r101 r102 r103 r104 r105 r106 r107 r108 r109 r110 r111 r112 r113 r114 r115 r116 r117 r118 r119 r120 r121 r122 r123 r124 r125 r126 r127 r128 r129 r130 r131 r132 r133 r134 r135 r136 r137 r138 r139 r140 r141 r142 r143 r144 r145 r146 r147 r148 r149 r150 r151 r152 r153 r154 r155 r156 r157 r158 r159 r160 r161 r162 r163 r164 r165 r166 r167 r168 r169 r170 r171 r172 r173 r174 r175 r176 r177 r178 r179 r180 r181 r182 r183 r184 r185 r186 r187 r188 r189 r190 r191 r192 r193 r194 r195 r196 r197 r198 r199 r200 r201 r202 r203 r204 r205 r206 r207 r208 r209 r210 r211 r212 r213 r214 r215 r216 r217 r218 r219 r220 r221 r222 r223 r224 r225 r226 r227 r228 r229 r230 r231 r232 r233 r234 r235 r236 r237 r238 r239 r240 r241 r242 r243 r244 r245 r246 r247 r248 r249 r250 r251 r252 r253 r254 r255 rp sp</Keywords>
-            <Keywords name="Keywords3">#define #extern #include #message</Keywords>
+            <Keywords name="Keywords3">#define #export #import #include #message</Keywords>
             <Keywords name="Keywords4">.align .byte .reserve .word</Keywords>
             <Keywords name="Keywords5"></Keywords>
             <Keywords name="Keywords6"></Keywords>

rtl/lxp32_alu.vhd

@@ -31,7 +31,6 @@ entity lxp32_alu is
 		cmd_cmp_i: in std_logic;
 		cmd_negate_op2_i: in std_logic;
 		cmd_and_i: in std_logic;
-		cmd_or_i: in std_logic;
 		cmd_xor_i: in std_logic;
 		cmd_shift_i: in std_logic;
 		cmd_shift_right_i: in std_logic;
@@ -62,22 +61,16 @@ signal cmp_carry: std_logic;
 signal cmp_s1: std_logic;
 signal cmp_s2: std_logic;
 
-signal and_result: std_logic_vector(31 downto 0);
-signal and_we: std_logic;
-signal or_result: std_logic_vector(31 downto 0);
-signal or_we: std_logic;
-signal xor_result: std_logic_vector(31 downto 0);
-signal xor_we: std_logic;
+signal logic_result: std_logic_vector(31 downto 0);
+signal logic_we: std_logic;
 
 signal mul_result: std_logic_vector(31 downto 0);
 signal mul_ce: std_logic;
 signal mul_we: std_logic;
 
-signal div_quotient: std_logic_vector(31 downto 0);
-signal div_remainder: std_logic_vector(31 downto 0);
+signal div_result: std_logic_vector(31 downto 0);
 signal div_ce: std_logic;
 signal div_we: std_logic;
-signal div_select_remainder: std_logic;
 
 signal shift_result: std_logic_vector(31 downto 0);
 signal shift_ce: std_logic;
@@ -97,7 +90,11 @@ assert MUL_ARCH="dsp" or MUL_ARCH="seq" or MUL_ARCH="opt"
 -- Add/subtract
 
 addend1<=unsigned(op1_i);
-addend2<=unsigned(op2_i) when cmd_negate_op2_i='0' else not unsigned(op2_i);
+
+addend2_gen: for i in addend2'range generate
+	addend2(i)<=op2_i(i) xor cmd_negate_op2_i;
+end generate;
+
 adder_result<=("0"&addend1)+("0"&addend2)+(to_unsigned(0,adder_result'length-1)&cmd_negate_op2_i);
 adder_we<=cmd_addsub_i and valid_i;
 
@@ -126,14 +123,15 @@ cmp_sg_o<=((cmp_s1 and cmp_s2 and cmp_carry) or
 	(not cmp_s1 and not cmp_s2 and cmp_carry) or
 	(not cmp_s1 and cmp_s2)) and not cmp_eq;
 
--- Logical functions
+-- Bitwise operations (and, or, xor)
+-- Note: (a or b) = (a and b) or (a xor b)
 
-and_result<=op1_i and op2_i;
-and_we<=cmd_and_i and valid_i;
-or_result<=op1_i or op2_i;
-or_we<=cmd_or_i and valid_i;
-xor_result<=op1_i xor op2_i;
-xor_we<=cmd_xor_i and valid_i;
+logic_result_gen: for i in logic_result'range generate
+	logic_result(i)<=((op1_i(i) and op2_i(i)) and cmd_and_i) or
+		((op1_i(i) xor op2_i(i)) and cmd_xor_i);
+end generate;
+
+logic_we<=(cmd_and_i or cmd_xor_i) and valid_i;
 
 -- Multiplier
 
@@ -191,27 +189,17 @@ gen_divider: if DIVIDER_EN generate
 			op1_i=>op1_i,
 			op2_i=>op2_i,
 			signed_i=>cmd_signed_i,
+			rem_i=>cmd_div_mod_i,
 			ce_o=>div_we,
-			quotient_o=>div_quotient,
-			remainder_o=>div_remainder
+			result_o=>div_result
 		);
 end generate;
 
 gen_no_divider: if not DIVIDER_EN generate
 	div_we<=div_ce;
-	div_quotient<=(others=>'0');
-	div_remainder<=(others=>'0');
+	div_result<=(others=>'0');
 end generate;
 
-process (clk_i) is
-begin
-	if rising_edge(clk_i) then
-		if div_ce='1' then
-			div_select_remainder<=cmd_div_mod_i;
-		end if;
-	end if;
-end process;
-
 -- Shifter
 
 shift_ce<=cmd_shift_i and valid_i;
@@ -233,34 +221,26 @@ shifter_inst: entity work.lxp32_shifter(rtl)
 
 result_mux_gen: for i in result_mux'range generate
 	result_mux(i)<=(adder_result(i) and adder_we) or
-		(and_result(i) and and_we) or
-		(or_result(i) and or_we) or
-		(xor_result(i) and xor_we) or
+		(logic_result(i) and logic_we) or
 		(mul_result(i) and mul_we) or
-		(div_quotient(i) and div_we and not div_select_remainder) or
-		(div_remainder(i) and div_we and div_select_remainder) or
+		(div_result(i) and div_we) or
 		(shift_result(i) and shift_we);
 end generate;
 
 result_o<=result_mux;
 
-result_we<=adder_we or and_we or or_we or xor_we or mul_we or div_we or shift_we;
+result_we<=adder_we or logic_we or mul_we or div_we or shift_we;
 we_o<=result_we;
 
 -- Pipeline control
 
 process (clk_i) is
 begin
 	if rising_edge(clk_i) then
-		if rst_i='1' then
+		if rst_i='1' or result_we='1' then
 			busy<='0';
-		else
-			if shift_ce='1' or mul_ce='1' or div_ce='1' then
-				busy<='1';
-			end if;
-			if result_we='1' then
-				busy<='0';
-			end if;
+		elsif shift_ce='1' or mul_ce='1' or div_ce='1' then
+			busy<='1';
 		end if;
 	end if;
 end process;

rtl/lxp32_cpu.vhd

@@ -14,7 +14,7 @@ entity lxp32_cpu is
 		DBUS_RMW: boolean;
 		DIVIDER_EN: boolean;
 		MUL_ARCH: string;
-		START_ADDR: std_logic_vector(29 downto 0)
+		START_ADDR: std_logic_vector(31 downto 0)
 	);
 	port(
 		clk_i: in std_logic;
@@ -42,6 +42,7 @@ architecture rtl of lxp32_cpu is
 
 signal fetch_word: std_logic_vector(31 downto 0);
 signal fetch_next_ip: std_logic_vector(29 downto 0);
+signal fetch_current_ip: std_logic_vector(29 downto 0);
 signal fetch_valid: std_logic;
 signal fetch_jump_ready: std_logic;
 
@@ -61,7 +62,6 @@ signal decode_cmd_cmp: std_logic;
 signal decode_cmd_jump: std_logic;
 signal decode_cmd_negate_op2: std_logic;
 signal decode_cmd_and: std_logic;
-signal decode_cmd_or: std_logic;
 signal decode_cmd_xor: std_logic;
 signal decode_cmd_shift: std_logic;
 signal decode_cmd_shift_right: std_logic;
@@ -89,8 +89,6 @@ signal interrupt_valid: std_logic;
 signal interrupt_vector: std_logic_vector(2 downto 0);
 signal interrupt_ready: std_logic;
 signal interrupt_return: std_logic;
-signal interrupts_enabled: std_logic_vector(7 downto 0);
-signal interrupts_blocked: std_logic_vector(7 downto 0);
 
 begin
 
@@ -109,6 +107,7 @@ fetch_inst: entity work.lxp32_fetch(rtl)
 
 		word_o=>fetch_word,
 		next_ip_o=>fetch_next_ip,
+		current_ip_o=>fetch_current_ip,
 		valid_o=>fetch_valid,
 		ready_i=>decode_ready,
 
@@ -124,6 +123,7 @@ decode_inst: entity work.lxp32_decode(rtl)
 
 		word_i=>fetch_word,
 		next_ip_i=>fetch_next_ip,
+		current_ip_i=>fetch_current_ip,
 		valid_i=>fetch_valid,
 		jump_valid_i=>execute_jump_valid,
 		ready_o=>decode_ready,
@@ -153,7 +153,6 @@ decode_inst: entity work.lxp32_decode(rtl)
 		cmd_jump_o=>decode_cmd_jump,
 		cmd_negate_op2_o=>decode_cmd_negate_op2,
 		cmd_and_o=>decode_cmd_and,
-		cmd_or_o=>decode_cmd_or,
 		cmd_xor_o=>decode_cmd_xor,
 		cmd_shift_o=>decode_cmd_shift,
 		cmd_shift_right_o=>decode_cmd_shift_right,
@@ -189,7 +188,6 @@ execute_inst: entity work.lxp32_execute(rtl)
 		cmd_jump_i=>decode_cmd_jump,
 		cmd_negate_op2_i=>decode_cmd_negate_op2,
 		cmd_and_i=>decode_cmd_and,
-		cmd_or_i=>decode_cmd_or,
 		cmd_xor_i=>decode_cmd_xor,
 		cmd_shift_i=>decode_cmd_shift,
 		cmd_shift_right_i=>decode_cmd_shift_right,
@@ -221,9 +219,7 @@ execute_inst: entity work.lxp32_execute(rtl)
 		jump_dst_o=>execute_jump_dst,
 		jump_ready_i=>fetch_jump_ready,
 
-		interrupt_return_o=>interrupt_return,
-		interrupts_enabled_o=>interrupts_enabled,
-		interrupts_blocked_o=>interrupts_blocked
+		interrupt_return_o=>interrupt_return
 	);
 
 scratchpad_inst: entity work.lxp32_scratchpad(rtl)
@@ -247,13 +243,14 @@ interrupt_mux_inst: entity work.lxp32_interrupt_mux(rtl)
 
 		irq_i=>irq_i,
 
-		interrupts_enabled_i=>interrupts_enabled,
-		interrupts_blocked_i=>interrupts_blocked,
-
 		interrupt_valid_o=>interrupt_valid,
 		interrupt_vector_o=>interrupt_vector,
 		interrupt_ready_i=>interrupt_ready,
-		interrupt_return_i=>interrupt_return
+		interrupt_return_i=>interrupt_return,
+
+		sp_waddr_i=>sp_waddr,
+		sp_we_i=>sp_we,
+		sp_wdata_i=>sp_wdata
 	);
 
 end architecture;

rtl/lxp32_dbus.vhd

@@ -54,6 +54,7 @@ signal sel: std_logic_vector(3 downto 0);
 signal sig: std_logic;
 signal rmw_mode: std_logic;
 
+signal dbus_rdata: std_logic_vector(31 downto 0);
 signal selected_byte: std_logic_vector(7 downto 0);
 
 begin
@@ -64,6 +65,13 @@ begin
 		if rst_i='1' then
 			we_out<='0';
 			strobe<='0';
+			sig<='-';
+			byte_mode<='-';
+			sel<=(others=>'-');
+			we<='-';
+			rmw_mode<='-';
+			dbus_adr_o<=(others=>'-');
+			dbus_dat_o<=(others=>'-');
 		else
 			we_out<='0';
 			if strobe='0' then
@@ -72,10 +80,10 @@ begin
 					sig<=cmd_signed_i;
 
 					dbus_adr_o<=addr_i(31 downto 2);
-					dbus_dat_o<=wdata_i;
 
 					if cmd_dbus_byte_i='0' then
 						byte_mode<='0';
+						dbus_dat_o<=wdata_i;
 						sel<="1111";
 
 						-- synthesis translate_off
@@ -85,11 +93,14 @@ begin
 						-- synthesis translate_on
 					else
 						byte_mode<='1';
+						dbus_dat_o<=wdata_i(7 downto 0)&wdata_i(7 downto 0)&
+							wdata_i(7 downto 0)&wdata_i(7 downto 0);
+
 						case addr_i(1 downto 0) is
-						when "00" => sel<="0001"; dbus_dat_o(7 downto 0)<=wdata_i(7 downto 0);
-						when "01" => sel<="0010"; dbus_dat_o(15 downto 8)<=wdata_i(7 downto 0);
-						when "10" => sel<="0100"; dbus_dat_o(23 downto 16)<=wdata_i(7 downto 0);
-						when "11" => sel<="1000"; dbus_dat_o(31 downto 24)<=wdata_i(7 downto 0);
+						when "00" => sel<="0001";
+						when "01" => sel<="0010";
+						when "10" => sel<="0100";
+						when "11" => sel<="1000";
 						when others =>
 						end case;
 					end if;
@@ -136,27 +147,24 @@ sel_rmw_gen: if RMW generate
 	dbus_sel_o<=(others=>'1');
 end generate;
 
-selected_byte_gen: for i in selected_byte'range generate
-	selected_byte(i)<=(dbus_dat_i(i) and sel(0)) or
-		(dbus_dat_i(i+8) and sel(1)) or
-		(dbus_dat_i(i+16) and sel(2)) or
-		(dbus_dat_i(i+24) and sel(3));
-end generate;
-
 process (clk_i) is
 begin
 	if rising_edge(clk_i) then
-		if byte_mode='0' then
-			rdata_o<=dbus_dat_i;
-		else
-			rdata_o(7 downto 0)<=selected_byte;
-			for i in rdata_o'high downto 8 loop
-				rdata_o(i)<=selected_byte(selected_byte'high) and sig;
-			end loop;
-		end if;
+		dbus_rdata<=dbus_dat_i;
 	end if;
 end process;
 
+selected_byte_gen: for i in selected_byte'range generate
+	selected_byte(i)<=(dbus_rdata(i) and sel(0)) or
+		(dbus_rdata(i+8) and sel(1)) or
+		(dbus_rdata(i+16) and sel(2)) or
+		(dbus_rdata(i+24) and sel(3));
+end generate;
+
+rdata_o<=dbus_rdata when byte_mode='0' else
+	X"000000"&selected_byte when selected_byte(selected_byte'high)='0' or sig='0' else
+	X"FFFFFF"&selected_byte;
+
 we_o<=we_out;
 busy_o<=strobe or we_out;