mpc83xx: Get rid of CONFIG_SYS_LBC_*

Except for one counter example, CONFIG_SYS_LBC_LBCR always has a value of either 0x00040000 or 0x00000000. CONFIG_SYS_LBC_MRTPR always has the value 0x20000000. CONFIG_SYS_LBC_LSDMR_{1,2,4,5} are not set for any mpc83xx board. CONFIG_SYS_LBC_LSRT is set by one board (to 0x32000000). To simplify the configuration files, hardcode the setting of these values for mpc83xx. Signed-off-by: Mario Six <[email protected]>
lukasauer · May 21, 2019 · 42c9a49 · 42c9a49
1 parent 133ec60
commit 42c9a49
Show file tree

Hide file tree

Showing 32 changed files with 43 additions and 195 deletions.
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
@@ -109,8 +109,9 @@ int dram_init(void)
 	msize = fixed_sdram();
 
 	/* Local Bus setup lbcr and mrtpr */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
 	sync();
 
 #ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC

diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -183,28 +183,36 @@ void sdram_init(void)
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
-
+	const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+				 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+				 LSDMR_WRC3 | LSDMR_CL3;
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
 
 	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->lbcr = 0x00000000;
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
+	/* LB sdram refresh timer, about 6us */
+	lbc->lsrt = 0x32000000;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller Machine Mode Register.
 	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
+
+	/* 0x68636733; precharge all the banks */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	/* 0x48636733; auto refresh */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 	asm("sync");
 	/*1 times*/
 	*sdram_addr = 0xff;
@@ -232,12 +240,13 @@ void sdram_init(void)
 	udelay(100);
 
 	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);

diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
@@ -129,8 +129,8 @@ int dram_init(void)
 
 	msize = setup_sdram();
 
-	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	out_be32(&lbc->lbcr, (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF));
+	out_be32(&lbc->mrtpr, 0x20000000);
 	sync();
 
 	gd->ram_size = msize;

diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
@@ -147,6 +147,9 @@ void sdram_init(void)
 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile fsl_lbc_t *lbc = &immap->im_lbc;
 	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
+	const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
+				 LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
+				 LSDMR_WRC3 | LSDMR_CL3;
 
 	puts("\n   SDRAM on Local Bus: ");
 	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@@ -156,22 +159,27 @@ void sdram_init(void)
 	 */
 
 	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
-	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
-	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->lbcr = 0x00000000;
+	/* LB refresh timer prescal, 266MHz/32 */
+	lbc->mrtpr = 0x20000000;
+	/* LB sdram refresh timer, about 6us */
+	lbc->lsrt = 0x32000000;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller Machine Mode Register.
 	 */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	/* 0x68636733; precharge all the banks */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	/* 0x48636733; auto refresh */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
 	asm("sync");
 	/*1 times*/
 	*sdram_addr = 0xff;
@@ -199,12 +207,13 @@ void sdram_init(void)
 	udelay(100);
 
 	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	/* 0x40636733; normal operation */
+	lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);

diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
@@ -100,8 +100,8 @@ int dram_init(void)
 	msize = fixed_sdram();
 
 	/* Local Bus setup lbcr and mrtpr */
-	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
-	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	out_be32(&lbc->lbcr, 0x00040000);
+	out_be32(&lbc->mrtpr, 0x20000000);
 	sync();
 
 	/* return total bus SDRAM size(bytes)  -- DDR */

diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
@@ -121,11 +121,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h
@@ -186,16 +186,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
-				| (0xFF << LBCR_BMT_SHIFT) \
-				| 0xF)	/* 0x0004ff0f */
-
-				/* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
-
 /* drivers/mtd/nand/raw/nand.c */
 #if defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_NAND_BASE		0xFFF00000

diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h
@@ -159,16 +159,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
-				| (0xFF << LBCR_BMT_SHIFT) \
-				| 0xF)	/* 0x0004ff0f */
-
-				/* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR	0x20000000  /*TODO */
-
 /* drivers/mtd/nand/nand.c */
 #define CONFIG_SYS_NAND_BASE		0xE2800000
 

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
@@ -116,11 +116,7 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-#define CONFIG_FSL_ELBC		1
+#define CONFIG_FSL_ELBC
 
 /*
  * FLASH on the Local Bus

diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
@@ -113,11 +113,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
@@ -113,11 +113,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00000000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
@@ -153,14 +153,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 /*
  * Serial Port
  */

diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
@@ -150,14 +150,6 @@
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 /*
  * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
  */

diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
@@ -250,19 +250,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024) /* Reserved for malloc */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
-				/* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT	0x32000000
-				/* LB refresh timer prescal, 266MHz/32*/
-#define CONFIG_SYS_LBC_MRTPR	0x20000000
-
 /*
  * Serial Port
  */

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
@@ -134,10 +134,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 
 /*

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
@@ -158,10 +158,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00000000
 #define CONFIG_FSL_ELBC		1
 
 /*

diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h
@@ -96,14 +96,6 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB */
 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Malloc size */
 
-/*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  no DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #undef CONFIG_SYS_LB_SDRAM	/* if board has SDRAM on local bus */
 
 /*

diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
@@ -110,11 +110,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-
 /*
  * FLASH on the Local Bus
  */

diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
@@ -36,15 +36,6 @@
 					 - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LBC_LBCR		(0x00040000 |\
-					 (0xFF << LBCR_BMT_SHIFT) |\
-					 0xF)
-
-#define CONFIG_SYS_LBC_MRTPR		0x20000000
-
 /*
  * Internal Definitions
  */

diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
 #define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */

diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
 #define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
 

diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h
@@ -341,11 +341,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 /* must be after the include because KMBEC_FPGA is otherwise undefined */
 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
 

diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h
@@ -289,11 +289,6 @@
 /* EEprom support */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LBC_LBCR	0x00000000
-
 #define CONFIG_SYS_APP1_BASE	0xA0000000    /* PAXG */
 #define	CONFIG_SYS_APP1_SIZE	256 /* Megabytes */
 #define CONFIG_SYS_APP2_BASE	0xB0000000    /* PINC3 */