Add loopback from PMOD0 8 to 10 in Verilator for Pinmux PWM test

This loopback can be physically present on the board for tests on the
FPGA, but must be modelled in Verilator simulation by directly
connecting the output from PMOD0 pin 8 to PMOD0 pin 10 in
`top_verilator.sv`. This will allow the Pinmux PWM test to pass in
simulation as well as on FPGA.

dv/verilator/top_verilator.sv

@@ -275,19 +275,21 @@ module top_verilator (input logic clk_i, rst_ni);
   // these signals are re-timed through a single register stage simply to prevent Verilator
   // warnings about circular combinational logic which assesses circularity at the net level
   // (i.e. `in_from_pins` and `out_to_pins`) rather than the bit level.
-  reg [4:0] loopback_q;
+  reg [5:0] loopback_q;
   always @(posedge clk_i) begin
     loopback_q <= {inout_to_pins[INOUT_PIN_AH_TMPIO8],
                    inout_to_pins[INOUT_PIN_AH_TMPIO1],
                    out_to_pins[OUT_PIN_MB10],  // mikroBUS CLick PWM -> PMOD0.1; PWM loopback
                    out_to_pins[OUT_PIN_MB7],   // mikroBUS Click TX -> RX; UART loopback.
-                   out_to_pins[OUT_PIN_MB4]};  // mikroBUS Click COPI -> CIPO; SPI loopback.
+                   out_to_pins[OUT_PIN_MB4],  // mikroBUS Click COPI -> CIPO; SPI loopback.
+                   inout_to_pins[INOUT_PIN_PMOD0_8]}; // PMOD0 8->10; PWM loopback
   end
   assign {inout_from_pins[INOUT_PIN_AH_TMPIO9],
           inout_from_pins[INOUT_PIN_AH_TMPIO0],
           inout_from_pins[INOUT_PIN_PMOD0_1],
           in_from_pins[IN_PIN_MB8],
-          in_from_pins[IN_PIN_MB3]} = loopback_q;
+          in_from_pins[IN_PIN_MB3],
+          inout_from_pins[INOUT_PIN_PMOD0_10]} = loopback_q;
 
   // Switch inputs have pull-ups and switches pull to ground when on, but in `top_sonata`
   // they are inverted, so 0 here means 'not pressed' or 'off'.