[tlul,rtl] Explicitly zero some integrity bits from tlul_adapter_reg #26390
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The existing behaviour of the tlul_rsp_intg_gen was to add rsp/data
integrity bits if their generation was enabled and pass through the
input integrity bits if not.
In some instantiations (in tlul_adapter_reg and tlul_adapter_dmi),
these bits are actually always zero. One consequence is missing
coverage in DV simulations. The problem is that e.g. the rsp_intg
signal is driven with a continuous assignment:
assign rsp_intg = tl_i.d_user.rsp_intg;
But the right hand side is zero, so constant and the assignment is not
marked as covered.
This commit adds a UserInIsZero parameter. If this is true then we
know the input d_user signal is zero and thus can wire the variable
directly to zero.
This removes the cover point but will not change RTL behaviour at all.
Signed-off-by: Rupert Swarbrick <[email protected]>
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The existing behaviour of the tlul_rsp_intg_gen was to add rsp/data integrity bits if their generation was enabled and pass through the input integrity bits if not.
In some instantiations (in tlul_adapter_reg and tlul_adapter_dmi), these bits are actually always zero. One consequence is missing coverage in DV simulations. The problem is that e.g. the rsp_intg signal is driven with a continuous assignment:
But the right hand side is zero, so constant and the assignment is not marked as covered.
This commit adds a UserInIsZero parameter. If this is true then we know the input d_user signal is zero and thus can wire the variable directly to zero.
This removes the cover point but will not change RTL behaviour at all.