[dv, aon_timer] Split intr_state prediction on intr_test write

[antmarzam]

To avoid wrongly updating an intr_state bit on intr_test write the TB predicts each field separetely depending on which bits were set on the intr_test write.

This avoids the mismatch that could happen if the TB was going to predict an intr_state field due to count > threshold and has set intr_status_exp but not yet predicted the value by the time an intr_test occurs.

[rswarbrick]

I'm a bit confused about this. I don't think any simulation time elapses between these lines, so how can something happen in the middle?

[antmarzam]

I'm a bit confused about this. I don't think any simulation time elapses between these lines, so how can something happen in the middle?

The issue is not within these lines, it's more related to how a TL-access (intr_test write) may predict the wrong intr_state if one of the bits in intr_status_exp was set to 1 (in another thread, like the count thread), but not yet predicted.
These lines just ensure that we only predict the bit that was set for the intr_test write.

This was reflected in a test in which the TB had the WDOG (bark) counting and it reached a point in which count > threshold, which set intr_status_exp[WDOG] = 1.
However, the TB takes some time from count > threshold until the prediction happens due to CDC and some flops in between.
So when the write to intr_test occurred, the predict method updated the wrong bit even though that bit wasn't even set in the data bus.

[rswarbrick]

Ah, thanks for the explanation. Looks sensible to me!