[ibex,fpga] Fix FPGA related Ibex counter issue

This commit fixes the reset logic of the Ibex counter module for the FPGA. Signed-off-by: Pascal Nasahl <[email protected]> (commit is original to earlgrey_1.0.0)
lowRISC · Dec 9, 2024 · c643d81 · c643d81
1 parent 20bf77b
commit c643d81
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Showing 2 changed files with 25 additions and 2 deletions.
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_counter.sv
@@ -55,8 +55,12 @@ module ibex_counter #(
   localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
   (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
 
-  // DSP output register requires synchronous reset.
-  `define COUNTER_FLOP_RST posedge clk_i
+  if (CounterWidth < 49) begin : g_dsp_counter
+    // DSP output register requires synchronous reset.
+    `define COUNTER_FLOP_RST posedge clk_i
+  end else begin : g_no_dsp_counter
+    `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
+  end
 `else
   logic [CounterWidth-1:0] counter_q;
 

diff --git a/hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch b/hw/vendor/patches/lowrisc_ibex/rtl/0002-Fix-fpga-counter-reset.patch
@@ -0,0 +1,19 @@
+diff --git a/ibex_counter.sv b/ibex_counter.sv
+index c78e510ee4..b4dc7ec347 100644
+--- a/ibex_counter.sv
++++ b/ibex_counter.sv
+@@ -55,8 +55,12 @@ module ibex_counter #(
+   localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
+   (* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
+
+-  // DSP output register requires synchronous reset.
+-  `define COUNTER_FLOP_RST posedge clk_i
++  if (CounterWidth < 49) begin : g_dsp_counter
++    // DSP output register requires synchronous reset.
++    `define COUNTER_FLOP_RST posedge clk_i
++  end else begin : g_no_dsp_counter
++    `define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
++  end
+ `else
+   logic [CounterWidth-1:0] counter_q;
+