[acrc, dv] Remove extra TL CSR agent

- TL agent for CSR is created by the CIP base classes and doesn't
  require to be manually created.
- Now the TB compiles, elaborates, execute the UVM build_phase and starts
  to run.
- The base sequence performs a write and read access to a register (only
  to test the CSR interface).
- Add tb.svg file to fix CI.

Signed-off-by: Martin Velay <[email protected]>

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env.sv

@@ -10,7 +10,6 @@ class ac_range_check_env extends cip_base_env #(
   );
   `uvm_component_utils(ac_range_check_env)
 
-  tl_agent tl_csr_agt;
   tl_agent tl_unfilt_agt;
   tl_agent tl_filt_agt;
 
@@ -28,11 +27,6 @@ endfunction : new
 function void ac_range_check_env::build_phase(uvm_phase phase);
   super.build_phase(phase);
 
-  // Create CSR TL agent
-  tl_csr_agt = tl_agent::type_id::create("tl_csr_agt", this);
-  uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agt*", "cfg", cfg.tl_csr_agt_cfg);
-  cfg.tl_csr_agt_cfg.en_cov = cfg.en_cov;
-
   // Create Unfiltered TL agent
   tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this);
   uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg);
@@ -47,13 +41,9 @@ endfunction : build_phase
 function void ac_range_check_env::connect_phase(uvm_phase phase);
   super.connect_phase(phase);
   if (cfg.en_scb) begin
-    tl_csr_agt.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export);
     tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export);
     tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export);
   end
-  if (cfg.is_active && cfg.tl_csr_agt_cfg.is_active) begin
-    virtual_sequencer.tl_csr_sqr = tl_csr_agt.sequencer;
-  end
   if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin
     virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer;
   end

hw/ip_templates/ac_range_check/dv/env/ac_range_check_env_cfg.sv

@@ -5,12 +5,10 @@
 class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block));
 
   // External component config objects
-  rand tl_agent_cfg tl_csr_agt_cfg;
   rand tl_agent_cfg tl_unfilt_agt_cfg;
   rand tl_agent_cfg tl_filt_agt_cfg;
 
   `uvm_object_utils_begin(ac_range_check_env_cfg)
-    `uvm_field_object(tl_csr_agt_cfg, UVM_DEFAULT)
     `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT)
     `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT)
   `uvm_object_utils_end
@@ -30,12 +28,15 @@ endfunction : new
 function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
   list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS;
   super.initialize(csr_base_addr);
-  // Create tl_csr agent config obj
-  tl_csr_agt_cfg = tl_agent_cfg::type_id::create("tl_csr_agt_cfg");
+
+  // TL Agent Configuration objects - Non RAL
   // Create tl_unfilt agent config obj
   tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg");
+  tl_unfilt_agt_cfg.if_mode = dv_utils_pkg::Host;
+
   // Create tl_filt agent config obj
   tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg");
+  tl_filt_agt_cfg.if_mode = dv_utils_pkg::Device;
 
   // Set num_interrupts
   begin

hw/ip_templates/ac_range_check/dv/env/ac_range_check_scoreboard.sv

@@ -12,12 +12,10 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
   // Local variables
 
   // TLM agent fifos
-  uvm_tlm_analysis_fifo #(tl_seq_item) tl_csr_fifo;
   uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo;
   uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo;
 
   // Local queues to hold incoming packets pending comparison
-  tl_seq_item tl_csr_q[$];
   tl_seq_item tl_unfilt_q[$];
   tl_seq_item tl_filt_q[$];
 
@@ -29,7 +27,6 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
   extern function void check_phase(uvm_phase phase);
 
   // Class specific methods
-  extern task process_tl_csr_fifo();
   extern task process_tl_unfilt_fifo();
   extern task process_tl_filt_fifo();
   extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
@@ -43,7 +40,6 @@ endfunction : new
 
 function void ac_range_check_scoreboard::build_phase(uvm_phase phase);
   super.build_phase(phase);
-  tl_csr_fifo    = new("tl_csr_fifo", this);
   tl_unfilt_fifo = new("tl_unfilt_fifo", this);
   tl_filt_fifo   = new("tl_filt_fifo", this);
   // TODO: remove once support alert checking
@@ -65,7 +61,6 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
       fork
         begin : main_thread
           fork
-            process_tl_csr_fifo();
             process_tl_unfilt_fifo();
             process_tl_filt_fifo();
           join
@@ -80,14 +75,6 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
   end
 endtask : run_phase
 
-task ac_range_check_scoreboard::process_tl_csr_fifo();
-  tl_seq_item item;
-  forever begin
-    tl_csr_fifo.get(item);
-    `uvm_info(`gfn, $sformatf("received tl_csr item:\n%0s", item.sprint()), UVM_HIGH)
-  end
-endtask : process_tl_csr_fifo
-
 task ac_range_check_scoreboard::process_tl_unfilt_fifo();
   tl_seq_item item;
   forever begin

hw/ip_templates/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv

@@ -8,7 +8,6 @@ class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #(
   );
   `uvm_component_utils(ac_range_check_virtual_sequencer)
 
-  tl_sequencer tl_csr_sqr;
   tl_sequencer tl_unfilt_sqr;
   tl_sequencer tl_filt_sqr;
 

hw/ip_templates/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv

@@ -34,5 +34,8 @@ task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD");
 endtask : dut_init
 
 task ac_range_check_base_vseq::ac_range_check_init();
-  `uvm_error(`gfn, "FIXME")
+  bit [TL_DW-1:0] tmp_test;
+  csr_wr(.ptr(ral.range_base[0]), .value(32'hABCD_1234));
+  csr_rd(.ptr(ral.range_base[0]), .value(tmp_test));
+  `uvm_info(`gfn, $sformatf("tmp_test=%0h", tmp_test), UVM_LOW)
 endtask : ac_range_check_init

hw/ip_templates/ac_range_check/dv/tb/tb.sv.tpl

@@ -76,9 +76,9 @@ module tb;
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
     uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_csr_agt*", "tl_csr_vif", tl_csr_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "tl_unfilt_vif", tl_unfilt_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "tl_filt_vif", tl_filt_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_csr_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "vif", tl_unfilt_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "vif", tl_filt_if);
     $timeformat(-12, 0, " ps", 12);
     run_test();
   end

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv

@@ -10,7 +10,6 @@ class ac_range_check_env extends cip_base_env #(
   );
   `uvm_component_utils(ac_range_check_env)
 
-  tl_agent tl_csr_agt;
   tl_agent tl_unfilt_agt;
   tl_agent tl_filt_agt;
 
@@ -28,11 +27,6 @@ endfunction : new
 function void ac_range_check_env::build_phase(uvm_phase phase);
   super.build_phase(phase);
 
-  // Create CSR TL agent
-  tl_csr_agt = tl_agent::type_id::create("tl_csr_agt", this);
-  uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agt*", "cfg", cfg.tl_csr_agt_cfg);
-  cfg.tl_csr_agt_cfg.en_cov = cfg.en_cov;
-
   // Create Unfiltered TL agent
   tl_unfilt_agt = tl_agent::type_id::create("tl_unfilt_agt", this);
   uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agt*", "cfg", cfg.tl_unfilt_agt_cfg);
@@ -47,13 +41,9 @@ endfunction : build_phase
 function void ac_range_check_env::connect_phase(uvm_phase phase);
   super.connect_phase(phase);
   if (cfg.en_scb) begin
-    tl_csr_agt.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export);
     tl_unfilt_agt.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export);
     tl_filt_agt.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export);
   end
-  if (cfg.is_active && cfg.tl_csr_agt_cfg.is_active) begin
-    virtual_sequencer.tl_csr_sqr = tl_csr_agt.sequencer;
-  end
   if (cfg.is_active && cfg.tl_unfilt_agt_cfg.is_active) begin
     virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agt.sequencer;
   end

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv

@@ -5,12 +5,10 @@
 class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block));
 
   // External component config objects
-  rand tl_agent_cfg tl_csr_agt_cfg;
   rand tl_agent_cfg tl_unfilt_agt_cfg;
   rand tl_agent_cfg tl_filt_agt_cfg;
 
   `uvm_object_utils_begin(ac_range_check_env_cfg)
-    `uvm_field_object(tl_csr_agt_cfg, UVM_DEFAULT)
     `uvm_field_object(tl_unfilt_agt_cfg, UVM_DEFAULT)
     `uvm_field_object(tl_filt_agt_cfg, UVM_DEFAULT)
   `uvm_object_utils_end
@@ -30,12 +28,15 @@ endfunction : new
 function void ac_range_check_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
   list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS;
   super.initialize(csr_base_addr);
-  // Create tl_csr agent config obj
-  tl_csr_agt_cfg = tl_agent_cfg::type_id::create("tl_csr_agt_cfg");
+
+  // TL Agent Configuration objects - Non RAL
   // Create tl_unfilt agent config obj
   tl_unfilt_agt_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agt_cfg");
+  tl_unfilt_agt_cfg.if_mode = dv_utils_pkg::Host;
+
   // Create tl_filt agent config obj
   tl_filt_agt_cfg = tl_agent_cfg::type_id::create("tl_filt_agt_cfg");
+  tl_filt_agt_cfg.if_mode = dv_utils_pkg::Device;
 
   // Set num_interrupts
   begin

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_scoreboard.sv

@@ -12,12 +12,10 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
   // Local variables
 
   // TLM agent fifos
-  uvm_tlm_analysis_fifo #(tl_seq_item) tl_csr_fifo;
   uvm_tlm_analysis_fifo #(tl_seq_item) tl_unfilt_fifo;
   uvm_tlm_analysis_fifo #(tl_seq_item) tl_filt_fifo;
 
   // Local queues to hold incoming packets pending comparison
-  tl_seq_item tl_csr_q[$];
   tl_seq_item tl_unfilt_q[$];
   tl_seq_item tl_filt_q[$];
 
@@ -29,7 +27,6 @@ class ac_range_check_scoreboard extends cip_base_scoreboard #(
   extern function void check_phase(uvm_phase phase);
 
   // Class specific methods
-  extern task process_tl_csr_fifo();
   extern task process_tl_unfilt_fifo();
   extern task process_tl_filt_fifo();
   extern task process_tl_access(tl_seq_item item, tl_channels_e channel, string ral_name);
@@ -43,7 +40,6 @@ endfunction : new
 
 function void ac_range_check_scoreboard::build_phase(uvm_phase phase);
   super.build_phase(phase);
-  tl_csr_fifo    = new("tl_csr_fifo", this);
   tl_unfilt_fifo = new("tl_unfilt_fifo", this);
   tl_filt_fifo   = new("tl_filt_fifo", this);
   // TODO: remove once support alert checking
@@ -65,7 +61,6 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
       fork
         begin : main_thread
           fork
-            process_tl_csr_fifo();
             process_tl_unfilt_fifo();
             process_tl_filt_fifo();
           join
@@ -80,14 +75,6 @@ task ac_range_check_scoreboard::run_phase(uvm_phase phase);
   end
 endtask : run_phase
 
-task ac_range_check_scoreboard::process_tl_csr_fifo();
-  tl_seq_item item;
-  forever begin
-    tl_csr_fifo.get(item);
-    `uvm_info(`gfn, $sformatf("received tl_csr item:\n%0s", item.sprint()), UVM_HIGH)
-  end
-endtask : process_tl_csr_fifo
-
 task ac_range_check_scoreboard::process_tl_unfilt_fifo();
   tl_seq_item item;
   forever begin

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_virtual_sequencer.sv

@@ -8,7 +8,6 @@ class ac_range_check_virtual_sequencer extends cip_base_virtual_sequencer #(
   );
   `uvm_component_utils(ac_range_check_virtual_sequencer)
 
-  tl_sequencer tl_csr_sqr;
   tl_sequencer tl_unfilt_sqr;
   tl_sequencer tl_filt_sqr;
 

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/seq_lib/ac_range_check_base_vseq.sv

@@ -34,5 +34,8 @@ task ac_range_check_base_vseq::dut_init(string reset_kind = "HARD");
 endtask : dut_init
 
 task ac_range_check_base_vseq::ac_range_check_init();
-  `uvm_error(`gfn, "FIXME")
+  bit [TL_DW-1:0] tmp_test;
+  csr_wr(.ptr(ral.range_base[0]), .value(32'hABCD_1234));
+  csr_rd(.ptr(ral.range_base[0]), .value(tmp_test));
+  `uvm_info(`gfn, $sformatf("tmp_test=%0h", tmp_test), UVM_LOW)
 endtask : ac_range_check_init

hw/top_darjeeling/ip_autogen/ac_range_check/dv/tb/tb.sv

@@ -76,9 +76,9 @@ module tb;
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
     uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shad_if);
     uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_csr_agt*", "tl_csr_vif", tl_csr_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "tl_unfilt_vif", tl_unfilt_if);
-    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "tl_filt_vif", tl_filt_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_csr_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_unfilt_agt*", "vif", tl_unfilt_if);
+    uvm_config_db#(virtual tl_if)::set(null, "*.env.tl_filt_agt*", "vif", tl_filt_if);
     $timeformat(-12, 0, " ps", 12);
     run_test();
   end