[hmac, dv] Update coverage exclusion file

This commit removes exclusions which were made obsolete in #25766
through minor RTL restructures. Two new exclusion pertaining to
missing else branches in `prim_sha2_pad` that cannot be covered have
been added (see #24692 for a discussion of these two exclusions).

Signed-off-by: Andrea Caforio <[email protected]>

hw/ip/hmac/dv/cov/hmac_cov_excl.el

@@ -4,36 +4,14 @@
 
 //==================================================
 // This file contains the Excluded objects
-// Generated By User: gdessouky
+// Generated By User: Andrea Caforio
 // Format Version: 2
-// Date: Sat Jul  6 04:05:21 2024
+// Date: Wed Feb 12 16:31:18 2025
 // ExclMode: default
 //==================================================
-CHECKSUM: "1683432060 1171249183"
+CHECKSUM: "3806569032 3159788697"
 INSTANCE: tb.dut.u_prim_sha2_512.gen_multimode_logic.u_prim_sha2_multimode.u_pad
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StLenHi->StFifoReceive "4->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StPad80->StFifoReceive "2->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StPad00->StFifoReceive "3->1"
-Fsm st_q "1171249183"
-ANNOTATION: "[INVALID] Intend to remove transition"
-Transition StLenLo->StFifoReceive "5->1"
-CHECKSUM: "1785966602"
-INSTANCE: tb.dut.u_tlul_adapter.u_rspfifo
-ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO"
-Assert DataKnown_A "assertion"
-CHECKSUM: "1785966602"
-INSTANCE: tb.dut.u_tlul_adapter.u_sramreqfifo
-ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO"
-Assert DataKnown_A "assertion"
-CHECKSUM: "3919502532"
-INSTANCE: tb.dut.u_tlul_adapter
-ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO"
-Assert rvalidHighReqFifoEmpty "assertion"
-ANNOTATION: "[INVALID] Disable this assertion as the FIFO is WO"
-Assert rvalidHighWhenRspFifoFull "assertion"
+ANNOTATION: "shaf_rready_i == 1'b0 cannot occur in the StLenHi and StLenLo states thus the missing else is unavoidable."
+Branch 8 "3400827115" "st_q" (17) "st_q StLenHi ,-,-,-,-,-,-,-,-,-,-,0,-"
+ANNOTATION: "shaf_rready_i == 1'b0 cannot occur in the StLenHi and StLenLo states thus the missing else is unavoidable."
+Branch 8 "3400827115" "st_q" (19) "st_q StLenLo ,-,-,-,-,-,-,-,-,-,-,-,0"