[hw,prim_ram_1r1w,rtl] Fix DFT response port

1. Fix output type to the response type 2. No need to cast from the underlying prim as they have the same type Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Jan 3, 2025 · 8d63d0b · 8d63d0b
1 parent a33614d
commit 8d63d0b
Showing 1 changed file with 2 additions and 6 deletions.
diff --git a/hw/ip/prim/rtl/prim_ram_1r1w_async_adv.sv b/hw/ip/prim/rtl/prim_ram_1r1w_async_adv.sv
@@ -54,7 +54,7 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
 
   // config
   input  ram_2p_cfg_t      cfg_i,
-  output ram_2p_cfg_t      cfg_rsp_o
+  output ram_2p_cfg_rsp_t  cfg_rsp_o
 );
 
 
@@ -92,7 +92,6 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
   logic [Width-1:0]        b_rdata_q,  b_rdata_d ;
   logic [TotalWidth-1:0]   b_rdata_sram ;
   logic [1:0]              b_rerror_q, b_rerror_d ;
-  prim_ram_1p_pkg::ram_1p_cfg_rsp_t cfg_rsp;
 
   prim_ram_1r1w #(
     .MemInitFile     (MemInitFile),
@@ -116,12 +115,9 @@ module prim_ram_1r1w_async_adv import prim_ram_2p_pkg::*; #(
     .b_rdata_o  (b_rdata_sram),
 
     .cfg_i,
-    .cfg_rsp_o  (cfg_rsp)
+    .cfg_rsp_o
   );
 
-  // DFT responeses need to match between prim_ram_1p and prim_ram_2p
-  assign cfg_rsp_o = ram_2p_cfg_rsp_t'(cfg_rsp);
-
   always_ff @(posedge clk_b_i or negedge rst_b_ni) begin
     if (!rst_b_ni) begin
       b_rvalid_sram_q <= 1'b0;