[racl] Unify the RACL error generation on ipgen'ed IPs

Racl errors have been unified on other IPs but this was missing. Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Feb 24, 2025 · 7c2f7e5 · 7c2f7e5
1 parent bfc20a9
commit 7c2f7e5
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Showing 3 changed files with 7 additions and 14 deletions.
diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler.sv.tpl b/hw/ip_templates/alert_handler/rtl/alert_handler.sv.tpl
@@ -14,7 +14,8 @@ module ${module_instance_name}
 % if racl_support:
   parameter bit          EnableRacl                                   = 1'b0,
   parameter bit          RaclErrorRsp                                 = EnableRacl,
-  parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[NumRegs] = '{NumRegs{0}},
+  parameter top_racl_pkg::racl_policy_sel_t RaclPolicySelVec[${module_instance_name}_reg_pkg::NumRegs] = 
+    '{${module_instance_name}_reg_pkg::NumRegs{0}},
 % endif
   // Compile time random constants, to be overriden by topgen.
   parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
@@ -49,8 +50,7 @@ module ${module_instance_name}
 % if racl_support:
   // RACL interface
   input  top_racl_pkg::racl_policy_vec_t          racl_policies_i,
-  output logic                                    racl_error_o,
-  output top_racl_pkg::racl_error_log_t           racl_error_log_o,
+  output top_racl_pkg::racl_error_log_t           racl_error_o,
 % endif
   // Escalation outputs
   // SEC_CM: ESC.INTERSIG.DIFF
@@ -100,7 +100,6 @@ module ${module_instance_name}
   % if racl_support:
     .racl_policies_i,
     .racl_error_o,
-    .racl_error_log_o,
   % endif
     // SEC_CM: BUS.INTEGRITY
     .fatal_integ_alert_o(loc_alert_trig[4])
@@ -337,8 +336,7 @@ module ${module_instance_name}
   `ASSERT_KNOWN(TlDValidKnownO_A,  tl_o.d_valid)
   `ASSERT_KNOWN(TlAReadyKnownO_A,  tl_o.a_ready)
 % if racl_support:
-  `ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
-  `ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
+  `ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)
 % endif
   `ASSERT_KNOWN(IrqAKnownO_A,      intr_classa_o)
   `ASSERT_KNOWN(IrqBKnownO_A,      intr_classb_o)

diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler_reg_wrap.sv.tpl b/hw/ip_templates/alert_handler/rtl/alert_handler_reg_wrap.sv.tpl
@@ -36,8 +36,7 @@ module ${module_instance_name}_reg_wrap import ${module_instance_name}_pkg::*; (
 % if racl_support:
   // RACL interface
   input  top_racl_pkg::racl_policy_vec_t racl_policies_i,
-  output logic                           racl_error_o,
-  output top_racl_pkg::racl_error_log_t  racl_error_log_o,
+  output top_racl_pkg::racl_error_log_t  racl_error_o,
 % endif
   // bus integrity alert
   output logic                 fatal_integ_alert_o
@@ -71,7 +70,6 @@ module ${module_instance_name}_reg_wrap import ${module_instance_name}_pkg::*; (
   % if racl_support:
     .racl_policies_i,
     .racl_error_o,
-    .racl_error_log_o,
   % endif
     .shadowed_storage_err_o(reg2hw_wrap.shadowed_err_storage),
     .shadowed_update_err_o(reg2hw_wrap.shadowed_err_update),

diff --git a/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl b/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl
@@ -42,8 +42,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
 
   // RACL interface
   input  top_racl_pkg::racl_policy_vec_t  racl_policies_i,
-  output logic                            racl_error_o,
-  output top_racl_pkg::racl_error_log_t   racl_error_log_o,
+  output top_racl_pkg::racl_error_log_t   racl_error_o,
 % endif
 
   // Interrupt Sources
@@ -263,7 +262,6 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
     // RACL interface
     .racl_policies_i,
     .racl_error_o,
-    .racl_error_log_o,
   % endif
 
     // SEC_CM: BUS.INTEGRITY
@@ -274,8 +272,7 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
   `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
   `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
 % if racl_support:
-  `ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
-  `ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
+  `ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)
 % endif
   `ASSERT_KNOWN(IrqKnownO_A, irq_o)
   `ASSERT_KNOWN(MsipKnownO_A, msip_o)