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[sw] Port rv_core_ibex_nmi_irq_test to devicetables
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As far as I can determine from the list of inter-module connections in
the Top HJSON, based on the Alert Handler's outgoing `esc_tx` signals,
the Darjeeling Alert handler uses the same escalation severity setup as
Earlgrey for now. Thus, all that needs doing to port this test is to
make the DIF initialisation and the single hard-coded alert go through
the devicetables API.

Signed-off-by: Alex Jones <[email protected]>
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AlexJones0 authored and jwnrt committed Feb 20, 2025
1 parent 022313c commit 60640d2
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Showing 2 changed files with 19 additions and 17 deletions.
3 changes: 2 additions & 1 deletion sw/device/tests/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -5344,13 +5344,14 @@ opentitan_test(
{
"//hw/top_earlgrey:fpga_cw310_sival": None,
"//hw/top_earlgrey:silicon_creator": None,
"//hw/top_darjeeling:sim_dv": None,
},
),
silicon = silicon_params(
tags = ["broken"],
),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
"//hw/top:dt",
"//sw/device/lib/dif:alert_handler",
"//sw/device/lib/dif:aon_timer",
"//sw/device/lib/dif:rv_core_ibex",
Expand Down
33 changes: 17 additions & 16 deletions sw/device/tests/rv_core_ibex_nmi_irq_test.c
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,11 @@
#include <stdbool.h>
#include <stdint.h>

#include "sw/device/lib/base/mmio.h"
#include "dt/dt_alert_handler.h" // Generated
#include "dt/dt_aon_timer.h" // Generated
#include "dt/dt_pwrmgr.h" // Generated
#include "dt/dt_rv_core_ibex.h" // Generated
#include "dt/dt_rv_timer.h" // Generated
#include "sw/device/lib/dif/dif_alert_handler.h"
#include "sw/device/lib/dif/dif_aon_timer.h"
#include "sw/device/lib/dif/dif_pwrmgr.h"
Expand All @@ -23,9 +27,6 @@
#include "sw/device/lib/testing/test_framework/ottf_isrs.h"
#include "sw/device/lib/testing/test_framework/ottf_main.h"

#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
#include "sw/device/lib/testing/autogen/isr_testutils.h"

OTTF_DEFINE_TEST_CONFIG();

typedef void (*isr_handler)(void);
Expand All @@ -41,6 +42,7 @@ static dif_pwrmgr_t pwrmgr;
static dif_rv_core_ibex_t rv_core_ibex;
static dif_aon_timer_t aon_timer;
static dif_alert_handler_t alert_handler;
static dt_pwrmgr_t kPwrmgrDt = kDtPwrmgrAon;

/**
* Program the alert handler to escalate on alerts upto phase 2 (i.e. reset)
Expand Down Expand Up @@ -83,7 +85,8 @@ static void alert_handler_config(void) {
.crashdump_escalation_phase = kDifAlertHandlerClassStatePhase3,
}};

dif_alert_handler_alert_t alerts[] = {kTopEarlgreyAlertIdPwrmgrAonFatalFault};
dt_alert_id_t alerts[] = {
dt_pwrmgr_alert_to_alert_id(kPwrmgrDt, kDtPwrmgrAlertFatalFault)};
dif_alert_handler_class_t alert_classes[] = {kDifAlertHandlerClassA};
dif_alert_handler_class_t classes[] = {kDifAlertHandlerClassA};
dif_alert_handler_config_t config = {
Expand Down Expand Up @@ -117,8 +120,7 @@ static void wdog_handler(void) {
CHECK_DIF_OK(dif_aon_timer_watchdog_stop(&aon_timer));
// In order to handle the NMI we need to acknowledge the interrupt status
// bit it at the peripheral side. Note that this test does not use the
// PLIC, so there is nothing to acknowledge on the PLIC side. We are hence
// not using the isr_testutils_aon_timer_isr function here.
// PLIC, so there is nothing to acknowledge on the PLIC side.
CHECK_DIF_OK(
dif_aon_timer_irq_acknowledge(&aon_timer, kDifAonTimerIrqWdogTimerBark));
}
Expand Down Expand Up @@ -253,18 +255,17 @@ void ottf_external_isr(uint32_t *exc_info) { ext_irq_fired = true; }
* Initialized all peripherals used in this test.
*/
void init_peripherals(void) {
mmio_region_t addr =
mmio_region_from_addr(TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR);
CHECK_DIF_OK(dif_rv_core_ibex_init(addr, &rv_core_ibex));
static_assert(kDtRvCoreIbexCount >= 1, "This test requires an Ibex core");
CHECK_DIF_OK(
dif_rv_core_ibex_init_from_dt((dt_rv_core_ibex_t)0, &rv_core_ibex));

addr = mmio_region_from_addr(TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR);
CHECK_DIF_OK(dif_aon_timer_init(addr, &aon_timer));
CHECK_DIF_OK(dif_aon_timer_init_from_dt(kDtAonTimerAon, &aon_timer));

addr = mmio_region_from_addr(TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR);
CHECK_DIF_OK(dif_alert_handler_init(addr, &alert_handler));
static_assert(kDtAlertHandlerCount >= 1, "This test needs an Alert Handler");
CHECK_DIF_OK(
dif_alert_handler_init_from_dt((dt_alert_handler_t)0, &alert_handler));

addr = mmio_region_from_addr(TOP_EARLGREY_PWRMGR_AON_BASE_ADDR);
CHECK_DIF_OK(dif_pwrmgr_init(addr, &pwrmgr));
CHECK_DIF_OK(dif_pwrmgr_init_from_dt(kPwrmgrDt, &pwrmgr));
}
/**
* This test do the following steps:
Expand Down

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