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[crypto] Trial division for RSA key generation. #6393

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[crypto] Trial division for RSA key generation.

[crypto] Trial division for RSA key generation. #6393

Triggered via pull request February 21, 2025 10:12
@jadephilipoomjadephilipoom
synchronize #21086
jadephilipoom:trial-div
Status Cancelled
Total duration 58m 40s
Artifacts 3

ci.yml

on: pull_request
Lint (quick)
4m 31s
Lint (quick)
Earl Grey for CW340  /  Build bitstream
4m 51s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
15m 31s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
36m 56s
Earl Grey for CW310 / Build bitstream
Lint (slow)
11m 25s
Lint (slow)
Build documentation
5m 12s
Build documentation
Airgapped build
12m 52s
Airgapped build
Verible lint
1m 9s
Verible lint
Run OTBN smoke Test
2m 36s
Run OTBN smoke Test
Run OTBN crypto tests
4m 11s
Run OTBN crypto tests
Verilated English Breakfast
8m 21s
Verilated English Breakfast
Verilated Earl Grey
53m 20s
Verilated Earl Grey
CW305's Bitstream
23m 10s
CW305's Bitstream
Build Docker Containers
5m 35s
Build Docker Containers
Build and test software
19m 48s
Build and test software
Build and test Darjeeling software
3m 38s
Build and test Darjeeling software
QEMU smoketest
2m 1s
QEMU smoketest
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
Hyper310 ROM_EXT Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
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Annotations

11 errors
Verilated English Breakfast
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/21086/merge' exists
Verilated Earl Grey
The operation was canceled.
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/21086/merge' exists
Earl Grey for CW340 / Build bitstream
The operation was canceled.
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/21086/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
The operation was canceled.
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/21086/merge' exists
Earl Grey for CW310 / Build bitstream
The operation was canceled.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
sw_build_test-test-results
73.9 KB
verilated_englishbreakfast
7.02 MB